Patents Examined by Anthony Ho
  • Patent number: 10411125
    Abstract: A semiconductor device includes a semiconductor structure including a first doped layer for forming a carrier channel having a carrier charge, a second doped layer having a conductivity type identical to a conductivity type of the first doped layer, a barrier layer arranged in proximity to the semiconductor structure via the second doped layer, wherein the barrier layer includes a partially doped layer having a conductivity type opposite to the conductivity type of the second doped layer, and a set of electrodes for providing and controlling the carrier charge in the carrier channel.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: September 10, 2019
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Koon Hoo Teo, Chenjie Tang
  • Patent number: 10410987
    Abstract: A display device including a display panel including a base layer, a circuit layer disposed on the base layer, and a pad part having a plurality of pads disposed on the base layer; and a driving chip disposed on the pad part and including a plurality of chip pads. The plurality of pads include a first pad having a smaller area than a corresponding chip pad among the plurality of chip pads and a second pad electrically connected to the circuit layer.
    Type: Grant
    Filed: June 11, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sujeong Kim, Hanho Park, Sangwon Yeo, Daegeun Lee, Joonsam Kim
  • Patent number: 10411083
    Abstract: A display device includes a substrate including a first display region, a second display region having an area smaller than that of the first display region, a third display region having an area smaller than that of the first display region, and a non-display region, a plurality of pixels provided in the first to third display regions, a power line which is connected to each of the plurality of pixels and applies a first power voltage to the plurality of pixels, and a fan-out line provided in the non-display region, the fan-out line applying a data signal to the plurality of pixels, where the power line includes an additional power line, a first power line, and disposed on the additional power line, and a second power line disposed on the first power line.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hee Rim Song, Kyung Hoon Kim, Mee Hye Jung, Min Jae Jeong, Seon Young Choi
  • Patent number: 10410918
    Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: September 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhiyuan Wu, Nikolaos Bekiaris, Mehul B. Naik, Jin Hee Park, Mark Hyun Lee
  • Patent number: 10403858
    Abstract: According to a method for manufacturing an organic electronic device, a sealing member (19) that includes a sealing substrate (15), an adhesive part (13) exhibiting adhesiveness and is provided on the sealing substrate (15), and a hygroscopic part (11) being a hygroscopic cured product provided on the adhesive part (13) is bonded to an organic electronic element (17).
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: September 3, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masato Shakutsui, Masaya Shimogawara, Shinichi Morishima
  • Patent number: 10403691
    Abstract: A display device including a display panel having a display area and a pad area, a circuit board connected to the pad area and configured to apply an electric signal to the display panel, a set frame configured to accommodate the display panel, and a buffer member between a surface of the display panel and the set frame. The buffer member may include a base and a protrusion adjacent the base and protrude from an edge portion of the display panel.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 3, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yunjae Kim
  • Patent number: 10391590
    Abstract: Embodiments herein may relate to a solder paste. The solder paste may include a solder powder and a flux. In embodiments, the flux may be a non-rosin based flux. The flux may further include a thixotropic agent (TA) that may be a non-polymer based TA. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventor: Kabir J. Mirpuri
  • Patent number: 10396050
    Abstract: Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material. The method may also include treating the dielectric material to render the dielectric material superomniphobic, and soldering the chip onto the bonding pad.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Campbell, Sarah K. Czaplewski, Joseph Kuczynski, Timothy J. Tofil
  • Patent number: 10383577
    Abstract: The present invention provides a portable sensing and operational device, which uses a sensing module to receive the sensing signal transmitted by the sensor and produce a sensing datum correspondingly. Then an operational circuit operates a first matrix and a second matrix according to the sensing datum. The first matrix corresponds to a plurality of maximum values; the second matrix corresponds to a plurality of minimum values. The operational circuit operates to generate at least a component by decomposing the first matrix and the second matrix. The component is provided to an output circuit for outputting the component to an electronic device.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: August 20, 2019
    Assignee: Huafan University
    Inventor: Kang-Ying Chen
  • Patent number: 10388691
    Abstract: A color stacked light emitting diode (LED) pixel is disclosed. The color stacked LED includes an LED pixel structure body, a base LED disposed on at least a portion of the LED pixel structure body, an intermediate LED disposed on the base LED, and a top LED disposed on the intermediate LED. The stacked LED may be an overlapping or a non-overlapping LED pixel. The LED pixel structure body may be a fin body or a nanowire body.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Srinivasa Banna, Deepak Nayak, Ajey P. Jacob
  • Patent number: 10388751
    Abstract: The present application discloses a semiconductor device and a method for forming an n-type conductive channel in a diamond using a heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method comprises: forming a diamond layer on a substrate; and depositing a ternary compound having a donor characteristic and graded components on an upper surface of the diamond layer to form a first donor layer, forming a graded heterojunction at an interface between the diamond layer and the first donor layer, forming two-dimensional electron gas at one side of the diamond layer adjacent to the graded heterojunction, and using the two-dimensional electron gas as the n-type conductive channel. The method enables a concentration and a mobility of carriers in the n-type diamond channel to reach 1013 cm?2 and 2000 cm2/V·s respectively.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 20, 2019
    Assignee: The 13ᵗʰ Research Institute Of China Electronics Technology Group Corporation
    Inventors: Jingjing Wang, Zhihong Feng, Cui Yu, Chuangjie Zhou, Qingbin Liu, Zezhao He
  • Patent number: 10388522
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 10381445
    Abstract: A silicon carbide semiconductor device includes: a drift layer in contact with a first main surface and having a first conductivity type; a body region located in the drift layer, in contact with the first main surface, and having a second conductivity type; and a protruding portion having the second conductivity type and connected to a bottom of the body region. A manufacturing method includes forming, in the drift layer of a silicon carbide substrate, by ion implantation, the body region, the protruding portion, a JTE region, and at least one guard ring region, each having the second conductivity type.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: August 13, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takashi Tsuno
  • Patent number: 10379092
    Abstract: An electronic sensing unit is used to receive an odorant sample and generate an electronic signature characterizing the sample received therein via a guiding unit that guides a first portion of the sample into an electronic sampling unit and a second portion of the sample towards an outlet. A control unit is used to receive data indicative of the signature generated by the sensing unit and data from user(s) indicative of olfactive descriptors characterizing the sample to which the users are exposed, thereby enabling creation of a data record including first and second characterizing data corresponding to the same sample. The database includes such data records, each being associated with a specific odorant sample, which may then be used to characterise, formulate, and/or create, a desired scent based on comparison of an electric signature generated for the scent and data records which signatures comply with some best compliance criterion.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: August 13, 2019
    Inventor: Alon Daniel Gafsou
  • Patent number: 10381515
    Abstract: An optoelectronic chip includes a semiconductor layer sequence including at least one n-doped semiconductor layer, at least one p-doped semiconductor layer, an active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer, wherein the p-doped semiconductor layer is electrically contacted by a p-connection contact, the n-doped semiconductor layer is electrically contacted by an n-connection contact, the semiconductor chip has at least two trenches, the p-connection contact is located within the first trench and the n-connection contact is located within the second trench, below the p-connection contact and within the first trench a first dielectric mirror element is arranged, which is electrically insulated, and below the n-connection contact and within the second trench and between the n-connection contact and the n-doped semiconductor layer, a second dielectric mirror element is arranged at least in regions, the second dielectric mirror element be
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 13, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Fabian Kopp, Attila Molnar
  • Patent number: 10374135
    Abstract: An embodiment provides a light emitting device package comprising: a package body; a first lead frame and a second lead frame, of which at least a part of each is inserted into the package body; and a light emitting device electrically flip bonded to the first lead frame and to the second lead frame, wherein the package body forms an electrode separation line between the first lead frame and the second lead frame, and the electrode separation line has at least two curved portions.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: August 6, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Keal Doo Moon, Sung Joo Oh
  • Patent number: 10371618
    Abstract: In one example embodiment, a filter condition measurement device features an engine data repository, one or more sensor units, and a measurement unit. The measurement system is configured to identify a first flow value corresponding to a sensed engine power value from the engine data repository, determine a filter coefficient for the filter as a function of the first flow value and the sensed delta-pressure value; identify a second engine power value from the plurality of stored engine power values and a second flow value corresponding to the second engine power value; and determine a second delta-pressure value for the air filter as a function of the filter coefficient and the second flow value.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 6, 2019
    Assignee: Bell Helicopter Textron Inc.
    Inventor: Alan H. Steinert
  • Patent number: 10374044
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane; a trench having a first side face, a second side face, and a bottom face; a first silicon carbide region of a first conductivity type; a second silicon carbide region and a third silicon carbide region of a second conductivity type, the third silicon carbide region and the second silicon carbide region sandwiching the trench; a sixth silicon carbide region of a second conductivity type in contact with the second side face and the bottom face; and a gate electrode in the trench. The first side face has a first region having a first inclination angle. The off angle of the first region with respect to a {0-33-8} face is no more than 2 degrees. A second inclination angle of the second side face is larger the first inclination angle.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 6, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke Iijima, Shinya Kyogoku
  • Patent number: 10367121
    Abstract: A method of manufacturing a package, the method comprising the steps of: preparing a resin compact having a recess, and including a pair of leads arranged at a bottom surface of the recess, a first resin body forming a lateral wall of the recess, and a second resin body arranged between the pair of leads; forming a reflective film entirely on at least the bottom surface of the recess and an inner surface of the lateral wall of the recess; and removing the reflective film formed on the pair of leads in the recess in the resin compact on which the reflective film has been formed.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 30, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Tadaaki Ikeda, Masaki Hayashi, Koji Abe, Kimihiro Miyamoto
  • Patent number: 10367065
    Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Guy M. Cohen