Patents Examined by Anthony Ho
  • Patent number: 10775356
    Abstract: A system and method for creating a scent database is described. An electronic sensing unit is used to receive an odorant sample and generate an electronic signature characterizing the sample received therein via a guiding unit that guides a first portion of the sample into an electronic sampling unit and a second portion of the sample towards an outlet. A control unit is used to receive data indicative of the signature generated by the sensing unit and data from user(s) indicative of olfactive descriptors characterizing the sample to which the users are exposed, enabling creation of a data record including first and second data corresponding to the same sample. The database includes data, each associated with a specific odorant sample, which may be used to characterise/formulate/create, a desired scent based on comparison of an electric signature generated for the scent and data records which signatures comply with best compliance criterion.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: September 15, 2020
    Inventor: Alon Daniel Gafsou
  • Patent number: 10777735
    Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel C. Edelstein, Bruce B. Doris, Henry K. Utomo, Theodorus E. Standaert, Nathan P. Marchack
  • Patent number: 10777723
    Abstract: The present disclosure discloses a light emitting diode (LED) package structure, a heat-dissipating substrate, a method for manufacturing an LED package structure, and a method for manufacturing a heat-dissipating substrate. The method for manufacturing the heat-dissipating substrate includes: providing a metal plate having a top surface and a bottom surface; implementing an etching process on the metal plate so as to form a first heat-dissipating block, a second heat-dissipating block, and a heat-dissipating plate spaced apart from each other; and filling an insulating material between the heat-dissipating plate and the first heat-dissipating block and between the heat-dissipating plate and the second heat-dissipating block so as to electrically isolate the heat-dissipating plate, the first heat-dissipating block, and the second heat-dissipating block from each other.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 15, 2020
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventor: Chen-Hsiu Lin
  • Patent number: 10770558
    Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Vincenzo Enea
  • Patent number: 10770466
    Abstract: A semiconductor device comprises laterally-neighboring word lines having respective word line caps thereon, an active region between the laterally-neighboring word lines and word line caps, an insulating material and a semiconductive material adjacent the word line caps, and a digit line contact between opposing substantially vertical surfaces of the semiconductive material, between opposing substantially vertical surfaces of the insulating material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps. A transition surface extending between and connecting the substantially horizontal surface and the substantially vertical surface of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact. Methods of forming the semiconductor device are also disclosed, as are electronic systems including the semiconductor device.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Naoyoshi Kobayashi, Osamu Fujita, Katsumi Koge
  • Patent number: 10770569
    Abstract: A transistor includes a semiconductive fin having a channel portion, a gate stack over the channel portion of the semiconductive fin, source and drain structures on opposite sides of the gate stack and adjoining the semiconductive fin, and a sidewall structure extending along sidewalls of a body portion of the source structure. The source structure has a curved top, and the source structure has a top portion protruding over a top of the sidewall structure.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lo, Shih-Hao Chen, Mu-Tsang Lin, Tung-Wen Cheng
  • Patent number: 10763452
    Abstract: The present disclosure relates to organic light-emitting diode display device, manufacturing method therefor and display apparatus. The organic light-emitting diode display device comprises: a substrate and a plurality of sub-pixel units arranged on the substrate. Each sub-pixel unit comprises a first electrode, a light-emitting functional layer and a second electrode arranged in this order on the substrate. A surface of the first electrode away from the substrate comprises a plurality of first grooves arranged in parallel with each other with equal width and equal spacing. A section of the first electrode is serrated. A depth of the plurality of first grooves is less than a maximum distance from the surface of the first electrode away from the substrate to the substrate. For some of the plurality of sub-pixel units, the plurality of first grooves have different widths, and spacings between adjacent two of the plurality of first grooves are different.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 1, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanhui Guo
  • Patent number: 10763320
    Abstract: An OLED display panel and a photomask are provided. The OLED display panel includes a plurality of pixel areas arranged in a matrix on a plane. Each of the pixel areas is defined by an electrode and an organic light emitting material. The pixel areas increase in size along a first direction and the pixel areas increase in size along a second direction perpendicular to the first direction. The application solves the problem of non-uniformity in displaying images, caused by a feed-through effect in existing arts.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 1, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Kaixiang Zhao
  • Patent number: 10763322
    Abstract: A first organic resin layer is formed over a first substrate; a first insulating film is formed over the first organic resin layer; a first element layer is formed over the first insulating film; a second organic resin layer is formed over a second substrate; a second insulating film is formed over the second organic resin layer; a second element layer is formed over the second insulating film; the first substrate and the second substrate are bonded; a first separation step in which adhesion between the first organic resin layer and the first substrate is reduced; the first organic resin layer and a first flexible substrate are bonded with a first bonding layer; a second separation step in which adhesion between the second organic resin layer and the second substrate is reduced; and the second organic resin layer and a second flexible substrate are bonded with a second bonding layer.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masakatsu Ohno, Hiroki Adachi, Satoru Idojiri, Koichi Takeshima
  • Patent number: 10763162
    Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10763176
    Abstract: One illustrative device disclosed includes a gate structure and a sidewall spacer positioned adjacent the gate structure, the sidewall spacer having an upper surface, wherein an upper portion of the gate structure is positioned above a level of the upper surface of the sidewall spacer. In this illustrative example, the device also includes a tapered upper surface on the upper portion of the gate structure and a gate cap, the gate cap being positioned above the tapered upper surface of the gate structure and above the upper surface of the sidewall spacer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 1, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Scott Beasor, Haiting Wang
  • Patent number: 10755928
    Abstract: A plurality of mandrels and silicon dioxide spacer structures are formed, with the spacer structures interdigitated between the mandrels. An organic planarization layer is applied, as are a thin oxide layer and a layer of photoresist patterned in hole tone over the oxide layer, thereby defining a domain. At least one hole is etched in the thin oxide layer and the organic planarization layer to expose a portion of a hard mask layer surface between the spacer structures. A selective polymer brush is applied, which grafts only to the exposed hard mask surface, followed by solvent rinsing the domain to remove ungrafted polymer brush. At least one precursor is infused to an etch resistant material into the polymer brush by a sequential infiltration synthesis process. The organic planarization layer is ashed to convert the infused precursor into oxide form to further enhance etch selectivity to the hard mask layer.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Kristin Schmidt, Yann Mignot, Martha Inez Sanchez, Daniel Paul Sanders, Nelson Felix, Ekmini Anuja De Silva
  • Patent number: 10755980
    Abstract: Laser light is converged at an object including a semiconductor substrate formed with a plurality of functional devices on a front surface, from a back surface of the semiconductor substrate, and while a distance between the front surface and a first converging point of the laser light is maintained at a first distance, whereby a first modified region is formed along the line. The laser light is converged at the object from the back surface, and while a distance between the front surface and a second converging point is maintained at a second distance, and while the second converging point is offset with respect to a position at which the first converging point is converged, whereby a second modified region is formed along the line. A predetermined portion including the back surface and at least the second modified region is removed.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: August 25, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takafumi Ogiwara, Yuta Kondoh
  • Patent number: 10756024
    Abstract: An electronic component module includes: a substrate including a conductive pattern; an electronic component provided to the substrate; a sealing portion covering the electronic component and substrate, and having an upper surface and a side surface that form an edge portion; a contact portion configured to be electrically connected with the conductive pattern, the contact portion exposed on a vertical surface continuous with the side surface of the sealing portion; a removal portion formed by removing the predetermined edge portion formed by the upper surface and the side surface of the sealing portion; and a shielding film covering the upper surface, the side surface and the contact portion of the sealing portion. The removal portion is a region allowing a conductive material to pass therethrough so that the contact portion is covered with the shielding film, the conductive material being scattered in vacuum atmosphere lower than atmospheric pressure.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kenzo Kitazaki, Takehiko Kai, Masaya Shimamura, Mikio Aoki, Jin Mikata, Taiji Ito
  • Patent number: 10756112
    Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The method includes alternately forming sacrificial layers and interlayer insulating layers on a semiconductor substrate. The method further includes forming a slit to expose the sacrificial layers by etching through the sacrificial layers and the interlayer insulating layers and forming interlayer openings by removing the exposed sacrificial layers. The method also includes depositing a conductive material in the interlayer openings and forming seams in which core patterns are deposited. The method additionally includes oxidizing a portion of the conductive material in the interlayer openings using a wet etching process and forming conductive patterns by removing the oxidized portion of the conductive material from the interlayer openings while leaving the seams intact.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Cheol Lee, Woo Jae Chung, Choung Sik Song
  • Patent number: 10755961
    Abstract: A method includes loading a wafer onto a robot arm, wherein a shield is disposed over the wafer, moving the wafer from a first location to a second location, and unloading the wafer from the robot arm.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Chen Wu, Tzu Wei Yu, Cheng Yu Wu
  • Patent number: 10749002
    Abstract: A semiconductor device includes a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET. The semiconductor device includes a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate. The semiconductor device includes a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate. Various example implementations of this type of semiconductor device provide a SiC power MOSFET with improved short-circuit capability and durability, with minimal impact on RDS-ON.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Martin Domeij
  • Patent number: 10748897
    Abstract: A semiconductor device is provided, which includes a first and second multichannel active patterns spaced apart from one another and extending in a first direction. The semiconductor device also includes first and second gate structures on the first and second multichannel active patterns, extending in a second direction and including first and second gate insulating films, respectively. Sidewalls of the first multichannel active pattern include first portions in contact with the first gate insulating film, second portions not in contact with the first gate insulating film, third portions in contact with the second gate insulating film, and fourth portions not in contact with the second gate insulating film. Additionally, a height of the first portions of the first multichannel active pattern is greater than a height of the third portions of the first multichannel active pattern.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Min Kim, Dong Won Kim
  • Patent number: 10748986
    Abstract: A semiconductor device structure and the formation method thereof are provided. The semiconductor device structure includes a semiconductor substrate and a first capacitor and a second capacitor over the semiconductor substrate. The first capacitor has a first capacitor dielectric layer, and the second capacitor has a second capacitor dielectric layer. The first capacitor dielectric layer is between the second capacitor dielectric layer and the semiconductor substrate. The first capacitor and the second capacitor are electrically connected in parallel. The first capacitor has a first linear temperature coefficient and a first quadratic voltage coefficient. The second capacitor has a second linear temperature coefficient and a second quadratic voltage coefficient. One or both of a first ratio of the first linear temperature coefficient to the second linear temperature coefficient and a second ratio of the first quadratic voltage coefficient to the second quadratic voltage coefficient is negative.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guo-Jyun Luo, Shiuan-Jeng Lin, Chiu-Hua Chung, Chen-Chien Chang, Han-Zong Pan
  • Patent number: 10749026
    Abstract: Provided are a semiconductor device including a desired snubber part in accordance with use of the semiconductor device and a method of manufacturing the semiconductor device. A snubber region having a snubber part is defined in a gate pad region defined on a side close to a first main surface of a semiconductor substrate. A p-type diffusion layer and an n-type column layer contacted to each other are formed in the snubber region. The p-type diffusion layer and the n-type column layer are formed as a parasitic capacitance of the snubber part while the n-type column layer is electrically coupled to a drain. The p-type diffusion layer, which extends in a Y-axis direction, is a resistance of the snubber part and electrically coupled to a source.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Yoshida, Tsuyoshi Kachi