Patents Examined by Anthony Ho
  • Patent number: 11374205
    Abstract: An object of the present invention is to provide a phase difference plate for an organic EL display device having excellent light resistance, an organic EL display device, and a method for producing a phase difference plate. The phase difference plate for an organic EL display device of an embodiment of the present invention is a phase difference plate for an organic EL display device having a phase difference layer formed from a composition containing a copolymer having both of a repeating unit A including a photo-alignment group and a repeating unit B including a moiety capable of expressing birefringence having reciprocal wavelength dispersion, in which the photo-alignment group includes a double bond structure of C?C or C?N.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: June 28, 2022
    Assignee: FUJIFILM Corporation
    Inventor: Shinichi Morishima
  • Patent number: 11374011
    Abstract: A method for manufacturing a DRAM includes: forming a hard mask layer on a substrate with an opening therein; forming a dielectric layer on a sidewall of the opening; forming a first barrier layer and a first conductor layer in the opening; performing a first dry etching and a first wet etching processes to respectively partially remove the first barrier layer and the first conductor layer, to expose the dielectric layer on upper sidewall; forming a second barrier layer in the opening; forming a mask layer in the opening to cover the second barrier layer; removing a part of the second barrier layer and the mask layer to expose the dielectric layer on the upper sidewall of the opening; and forming a second conductor layer in the opening.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: June 28, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Akira Kuroda, Hsin-Ya Wang, Chang-Han Tsai, Ming-Ting Cai
  • Patent number: 11373936
    Abstract: A flat no-leads package, the flat no-leads package includes a leadframe for electrically connecting an integrated circuit (IC) chip which in a mounted configuration is arranged in a center portion of the flat no-leads package. The leadframe has at least one RF lead pin; and an isolating encapsulation which is at least partially encapsulating the leadframe such that contact surfaces of the leadframe are electrically contactable at least from a bottom side of the flat no-leads package; wherein at least one of the RF lead pin has a first and second contact surfaces. A cross-section of the RF lead pin increases from the first contact surface to the second contact surface both in a horizontal direction and in a direction vertical thereto. Further, a printed circuit board having a flat no-leads package and a measurement device having a flat no-leads package are provided.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 28, 2022
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Simon Reiss, Chris Haehnlein, Robert Ziegler
  • Patent number: 11374009
    Abstract: A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: June 28, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Yu-Ting Lin
  • Patent number: 11367735
    Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongsoon Lim, Daeseok Byeon
  • Patent number: 11367859
    Abstract: A light emitting device includes a first electrode, a second electrode, and an emissive layer between the first and second electrodes. The emissive layer comprises quantum dots that are capable of producing circularly polarized luminescence. The quantum dots are chiral structured perovskite quantum dots, each comprising a core having a chiral crystal structure.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: June 21, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Iain Hamilton, Tim Michael Smeeton
  • Patent number: 11359106
    Abstract: The present disclosure relates to an inkjet printing ink and application thereof. In one aspect, the inkjet printing ink includes a crosslinking type organic host material, an organic doped luminescent material, a surface tension modifier, a viscosity modifier, and a solvent. On the other aspect, the present disclosure provides printing the inkjet printing ink on a substrate of a display panel to be prepared, performing drying process, and performing baking process at 120° C. to form an organic light emitting layer. Therefore, avoiding the problem of mutual dissolution of the organic light emitting layer and the electron transport layer when the electron transport layer is printed on the organic light emitting layer, avoiding damage to the organic light emitting layer, realize an inkjet printing process of the organic electron transport layer, thereby reducing the cost of manufacturing.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 14, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Shipan Wang
  • Patent number: 11362161
    Abstract: A display device includes pixels. Each of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node. A channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young In Hwang, Ji Hye Kong, Suk Hoon Ku, Sung Wook Kim, Jin A Lee, Yun Sik Joo
  • Patent number: 11357234
    Abstract: A food safety quality and performance monitoring system is provided, which is part of Industry 4.0 factory monitoring, including: a slaughter production line monitoring module recording a first monitoring information including quantity, voltage, temperature and humidity, time, and the like; a processing line monitoring module recording a second monitoring information including quantity, temperature and humidity, time, metal detection, and the like; an intelligent central monitoring server storing the first monitoring information and the second monitoring information and allowing a user to register and log in; and a human-machine interface facilitating the security and performance monitoring of the food production line. A food safety quality and performance monitoring method is further provided.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 14, 2022
    Assignee: Yuan Jin Chuang Enterprise Co., Ltd
    Inventors: Hung-Yuan Wu, Meng-Hui Lin
  • Patent number: 11362063
    Abstract: A semiconductor device is disclosed including a wire bonded die stack where the bond wires skip dies in the die stack to provide bond wires having a long length. In one example, the semiconductor dies are stacked on top of each other with offsets along two orthogonal axes so that the dies include odd numbered dies interspersed and staggered with respect to even numbered dies only one of the axes. Wire bonds may be formed between the odd numbered dies, skipping the even numbered dies, and wire bonds may be formed between the even numbered dies, skipping the odd numbered dies. The long length of the bond wires increases an inductance of the wire bonds relative to parasitic capacitance of the semiconductor dies, thereby increasing signal path bandwidth of the semiconductor device.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 14, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xinzhi Xing, John T. Contreras
  • Patent number: 11362296
    Abstract: A device includes first and second electrodes that are at least partially transparent in a spectral domain; an electroluminescent layer that lies between the first and second electrodes suitable for emitting electromagnetic radiation in the spectral domain, the electromagnetic radiation being circularly polarized in a first polarization direction; a structured substrate, the first electrode lying between the structured substrate and the electroluminescent layer, the structured substrate including features that are reflective in the spectral domain, and that possess a hollow geometric shape configured so that electromagnetic radiation that passes through the first electrode is reflected from the reflective features while preserving the first polarization direction, a filler material that is transparent in the spectral domain and that is arranged to fill the reflective features so that the structured substrate has a planar surface.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: June 14, 2022
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Etienne Quesnel, Marianne Consonni, Sylvia Meunier, Benoit Racine
  • Patent number: 11355496
    Abstract: A semiconductor device comprises a semiconductor substrate, and a pair of metal gates extends upwards from the semiconductor substrate. First and second channel regions are disposed between inner sidewalls of the pair of metal gates. First and second drain regions are disposed between the inner sidewalls of the pair of metal gates and are disposed directly over the first and second channel regions, respectively. First and second source regions are disposed between the inner sidewalls of the pair of metal gates directly below the first and second channel regions, respectively. A capacitor dielectric structure is disposed below the first and second source regions. A bottom capacitor electrode is disposed below the capacitor dielectric. The capacitor dielectric structure separates the first and second drain regions from the bottom capacitor electrode.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mauricio Manfrini, Chung-Te Lin
  • Patent number: 11355672
    Abstract: One embodiment comprises: a semiconductor substrate; a pattern layer disposed on the semiconductor substrate and comprising a plurality of patterns that are spaced apart from each other; a nitride semiconductor layer disposed on the pattern layer; and a semiconductor substrate disposed on the nitride semiconductor layer and comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, wherein the thermal conductivity of the pattern layer is higher than the thermal conductivity of the semiconductor substrate and the thermal conductivity of the semiconductor structure.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 7, 2022
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventor: Youn Joon Sung
  • Patent number: 11355709
    Abstract: A light-emitting device and a manufacturing method thereof are disclosed. The manufacturing method of the light-emitting device includes: forming a function layer that has a first surface; performing plasma treatment on the first surface of the function layer; and forming a perovskite-type light-emitting layer on the first surface treated by the plasma treatment.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 7, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Dengbao Han
  • Patent number: 11355451
    Abstract: In one example, a semiconductor device comprises a substrate comprising a conductive structure, a first electronic component over the substrate, an encapsulant over the substrate and contacting a lateral side of the first electronic component, a shield over the encapsulant and contacting a lateral side of the encapsulant and a portion of a lateral side of the substrate, and a communication structure coupled with the substrate. The substrate comprises a vertical groove side and a horizontal groove side defining a groove in the substrate, wherein a portion of the groove is uncovered by the shield. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: June 7, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Ji Hoon Oh, Dong Hyun Bang, Soo Jin Shin, Young Ik Kwon, Tae Kyeong Hwang, Min Jae Lee, Min Jae Kong
  • Patent number: 11348936
    Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 31, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang Chen, Lei Xue, Wei Liu, Shi Qi Huang
  • Patent number: 11349033
    Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 31, 2022
    Assignee: Kioxia Corporation
    Inventors: Tomoki Ishimaru, Shinji Mori, Kazuhiro Matsuo, Keiichi Sawa, Akifumi Gawase
  • Patent number: 11348976
    Abstract: A display panel having a plurality of subpixels is provided. The display panel includes a base substrate; a plurality of light emitting elements on the base substrate; and a quantum dot layer on a side of the plurality of light emitting elements away from the base substrate. A respective one of the plurality of light emitting elements includes a first light emitting layer and a second light emitting layer sequentially stacked. The first light emitting layer is configured to emit a first light of a first wavelength range. The second light emitting layer is configured to emit a second light of a second wavelength range. The plurality of light emitting elements are configured to respectively emit a composite light. The quantum dot blocks of different colors are configured to respectively convert the composite light into light of different colors respectively in different subpixels.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 31, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Qingyu Huang, Huajie Yan, Liangliang Kang, Fudong Chen, Zhiqiang Jiao
  • Patent number: 11342352
    Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 24, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang Chen, Lei Xue, Wei Liu, Shi Qi Huang
  • Patent number: 11342334
    Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sai-Hooi Yeong, Chi On Chui, Yu-Ming Lin