Patents Examined by Anthony Ho
  • Patent number: 12764989
    Abstract: A field effect transistor, comprising: a substrate and a superlattice of stacked conducting channels on the substrate; a source and a drain spaced-apart from each other on the superlattice; alternating castellations and trenches formed in the superlattice between the source and the drain, wherein the castellations have sidewalls that cut-down through the superlattice to form the trenches and edges of the stacked conducting channels that terminate at the sidewalls; a fringe field dielectric that fills lower volumes of the trenches up to a height on the sidewalls that is higher than first edges of first conducting channels among the stacked conducting channels, such that the fringe field dielectric is adjacent to the first edges; and a gate electrode overlaying the fringe field dielectric and the castellations such that the gate electrode is not adjacent to the first edges.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: October 13, 2026
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Kevin M. Frey, Ken Nagamatsu, Josephine Chang, Robert S. Howell
  • Patent number: 12765225
    Abstract: A display device includes a substrate including a non-transmissive area and a transmissive area, where the non-transmissive area has a first emission area, and the transmissive area has a second emission area. The display device further includes a first light emitting element disposed in the non-transmissive area and including a first anode electrode, a second light emitting element disposed in the transmissive area and including a second anode electrode, a thin film transistor disposed in the non-transmissive area and configured to drive at least the second light emitting element, and a transparent electrode electrically connecting the thin film transistor to the second anode electrode of the second light emitting element. Further, the structures of the first anode electrode and the second anode electrode are different from each other.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: October 13, 2026
    Assignee: LG DISPLAY CO., LTD.
    Inventors: TaeJoon Song, ChulHo Kim, JungSik Jo, YunHo Kook
  • Patent number: 12765214
    Abstract: Disclosed are a display substrate and a method for manufacturing the same, and a display device, belonging to the technical field of display. The display substrate includes: a base substrate, an electroluminescent device layer on the base substrate, and a light-absorbing layer on a light-emitting side of the electroluminescent device layer, wherein the electroluminescent device layer is configured to emit initial light of a first color, wherein the initial light forms target light after passing through the light-absorbing layer, and a full width at half maximum of an emission spectrum of the initial light is greater than a full width at half maximum of an emission spectrum of the target light. According to the present disclosure, the display device is provided with a wider color gamut.
    Type: Grant
    Filed: April 11, 2024
    Date of Patent: October 13, 2026
    Assignees: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhuo Chen, Siyi Yin
  • Patent number: 12765250
    Abstract: The present invention relates to a process for producing a layer of a crystalline A/M/X material, which crystalline A/M/X material comprises a compound of formula [A]a[M]b[X]c, wherein: [M] comprises one or more first cations, which one or more first cations are metal or metalloid cations; [A] comprises one or more second cations; [X] comprises one or more halide anions; a is an integer from 1 to 6; b is an integer from 1 to 6; and c is an integer from 1 to 18, wherein the process comprises disposing on a substrate a precursor composition comprising: (a) a first precursor compound comprising a first cation (M), which first cation is a metal or metalloid cation; and (b) a solvent, and wherein the solvent comprises: (i) a non-polar organic solvent which is a hydrocarbon solvent, a chlorohydrocarbon solvent or an ether solvent; and (ii) a first organic amine comprising at least three carbon atoms. Also described are compositions useful in the process of the invention.
    Type: Grant
    Filed: March 18, 2024
    Date of Patent: October 13, 2026
    Assignee: OXFORD PHOTOVOLTAICS LIMITED
    Inventors: Henry James Snaith, Bernard Wenger, Pabitra Kumar Nayak, Nakita Kimberly Noel
  • Patent number: 12764950
    Abstract: A semiconductor device may include a gate structure including insulating layers and conductive layers alternately stacked, a channel layer passing through the gate structure, an insulating core disposed in the channel layer, and a capping layer including a capping pattern disposed in the channel layer and a capping liner disposed between the capping pattern and the insulating core and extending between the channel layer and the capping pattern, wherein the capping liner and the capping pattern may include impurities having different concentrations.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: October 13, 2026
    Assignee: SK hynix Inc.
    Inventors: Hee Do Na, Hee Soo Kim, Yoon Soo Oh, Chang Soo Lee, Chul Young Ham
  • Patent number: 12757697
    Abstract: A substrate liquid processing method includes preparing a substrate having a recess on a surface thereof, a seed layer being formed on a surface of the recess; bringing a first pretreatment liquid, containing a reducing agent, a pH adjuster, and an additive configured to accelerate or inhibit an electroless plating reaction, into contact with the seed layer; and precipitating, after the bringing of the first pretreatment liquid into contact with the seed layer, a plating metal in the recess by supplying a first electroless plating liquid to the recess.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: October 6, 2026
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Keiichi Fujita, Takashi Tanaka
  • Patent number: 12757743
    Abstract: A press pack power semiconductor device can include a housing, a semiconductor, and a locator strip deformed into a ring-like shape to concentrically fit within the housing and concentrically locate at least part of the semiconductor therein. The locator strip can include a first plurality of regions regularly interspersed with a second plurality of regions along a length of the locator strip, and each of the first plurality of regions can have a first cross-sectional area that can be smaller than a second cross-sectional area of each of the second plurality of regions.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: October 6, 2026
    Assignee: Littelfuse, Inc.
    Inventors: Thomas Spann, Joseph Geo
  • Patent number: 12757472
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a lower electrode on a substrate, a metal oxide on the lower electrode, a buffer on the metal oxide, an oxide channel in the buffer, a gate insulating layer in the oxide channel, a gate electrode in the gate insulating layer, and an upper electrode on the gate electrode, and the buffer may include a silicide material.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: October 6, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeeeun Yang, Sangwook Kim, Euntae Kim, Kwanghee Lee, Moonil Jung
  • Patent number: 12757505
    Abstract: An image sensor comprises a plurality of image sensing pixels arranged to form a sensor array. Each image sensing pixel of the plurality of image sensing pixels comprises a semiconductor photodetector connected to a photosensitive region that comprises a photon reception area configured to receive photons to facilitate image capture. For at least a particular image sensing pixel of the plurality of image sensing pixels, the length or the width of the photon reception area is smaller than about 80% of a pixel pitch measurement between the particular image sensing pixel and an adjacent image sensing pixel, which contributes to reduced volume of the photosensitive region and mitigated sensor noise. A space between the photosensitive region of the particular image sensing pixel and the photosensitive region of the adjacent image sensing pixel comprises at least one oxide layer and/or at least one metal layer.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: October 6, 2026
    Assignee: Microsoft Technology Licesning, LLC
    Inventors: Minseok Oh, Rui Jin
  • Patent number: 12751133
    Abstract: Provided is an organic electroluminescent device. The organic electroluminescent device includes an anode, a cathode, and a hole transporting region disposed between the anode and the cathode; the hole transporting region includes a first organic layer; the first organic layer contains a first p-type dopant and a second p-type dopant; the first p-type dopant is different from the second p-type dopant. The electroluminescent device containing at least two different p-type dopants in the first organic layer in the hole transporting region can maintain a high external quantum efficiency and achieve the great reduction in voltages and the significant improvement in lifetimes, thereby improving the comprehensive performance of the device. Further provided is an electronic assembly containing the organic electroluminescent device.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: September 29, 2026
    Assignee: BEIJING SUMMER SPROUT TECHNOLOGY CO., LTD.
    Inventors: Menglan Xie, Huiqing Pang, Chi Yuen Raymond Kwong, Jing Wang
  • Patent number: 12740467
    Abstract: A die includes a plurality of pillar bumps configured to electrically connect the die to a substrate. The plurality of pillar bumps includes at least one first pillar bump having a first total pillar bump height. The at least one first pillar bump includes a first pillar having a first pillar height and a first solder cap having a first solder cap height. The plurality of pillar bumps includes at least one second pillar bump having a second pillar height substantially equal to the first total pillar bump height. The at least one second pillar bump includes a second pillar having a second pillar height and a second solder cap having a second solder cap height. The second pillar height is greater than the first pillar height, and the second solder cap height is less than the first solder cap height.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: September 15, 2026
    Assignee: QUALCOMM INCORPORATED
    Inventors: Wei Hu, Dongming He, Zhaozhi Li, Yangyang Sun
  • Patent number: 12740230
    Abstract: A light-emitting device including a substrate; a first electrode disposed on the substrate; a second electrode facing the first electrode; an interlayer disposed between the first electrode and the second electrode, wherein the interlayer includes an emission layer; and an antioxidant, wherein the first electrode is a cathode, and the second electrode is an anode.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: September 15, 2026
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Juyon Lee, Yonghwi Kim, Jonghoon Kim, Myoungjin Park, Junwoo Park
  • Patent number: 12740314
    Abstract: A light-emitting device including a first electrode, a second electrode facing the first electrode, and an interlayer between the first electrode and the second electrode and including an emission layer is provided. The emission layer includes a sensitizer and an emitter and a spectral overlap integral of an emission spectrum of the sensitizer and an absorption spectrum of the emitter is at least 1×1013 M?1 cm4. A highest occupied molecular orbital (HOMO) energy level of the sensitizer is greater than a HOMO energy level of the emitter, and the spectral overlap integral is evaluated by Equation 1: J ? ( ? ) = ? 0 ? ? ? ( ? ) ? ? 4 ? F D ( ? ) ? d ? ? .
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: September 15, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyosup Shin, Tsuyoshi Naijo, Sungsoo Bae, Hojung Syn, Jiyoung Lee, Changwoong Chu
  • Patent number: 12733332
    Abstract: The present disclosure provides a quantum dot light-emitting diode, a manufacturing method thereof, and a quantum dot film. The quantum dot light-emitting diode includes a first electrode, a second electrode, and a quantum dot light-emitting layer. The quantum dot light-emitting layer is disposed between the first electrode and the second electrode. The quantum dot light-emitting layer includes a first quantum dot and a second quantum dot, and an absolute value of a difference between a photoluminescence peak wavelength of the first quantum dot and a photoluminescence peak wavelength of the second quantum dot is less than or equal to 10 nm.
    Type: Grant
    Filed: December 3, 2023
    Date of Patent: September 8, 2026
    Assignee: TCL TECHNOLOGY GROUP CORPORATION
    Inventors: Likuan Zhou, Yixing Yang
  • Patent number: 12733457
    Abstract: Various embodiments of improved systems and methods are provided herein to monitor process chemicals used in a semiconductor process. More specifically, new semiconductor processing systems and methods that utilize infrared (IR) spectroscopy techniques are provided herein to monitor the composition and/or concentration of process chemicals utilized to process a substrate and/or the by-products produced during substrate processing. By monitoring the process chemicals and/or the by-products in real-time, the systems and methods described herein can be used to provide better process control and/or end-point detection for a wide variety of semiconductor processes.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: September 8, 2026
    Assignee: Tokyo Electron Limited
    Inventors: Sean Berglund, Michael Carcasi, Robert Brandt, Joshua Hooge, Ankur Agarwal, Ryan Burns
  • Patent number: 12733527
    Abstract: The present invention relates to an apparatus for bonding clips, a method of bonding clips, and a semiconductor package including semiconductor chips to which the clips are bonded using the method, and more particularly, to an apparatus for bonding clips, a method of bonding clips, and a semiconductor package including semiconductor chips to which the clips are bonded using the method, wherein the clips are sequentially bonded to the semiconductor chips by 1 unit so that a pitch difference between a lead frame array and a clip array is separately corrected to be the same and thereby, misalignment may be minimized so as to increase bonding accuracy of the clips to the semiconductor chips.
    Type: Grant
    Filed: March 26, 2024
    Date of Patent: September 8, 2026
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, Ji Won Choi
  • Patent number: 12720898
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a first integrated circuit (IC) die stacked with a second IC die. The first IC die includes a plurality of photodetectors disposed within a first substrate. The second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate. The semiconductor capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a doped capacitor region. The first capacitor electrode overlies the second substrate and comprises a protrusion disposed in the second substrate. The capacitor dielectric layer is disposed between the first capacitor electrode and the second substrate. The doped capacitor region is disposed within the second substrate and underlies the first capacitor electrode. The plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: August 25, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shen-Hui Hong, Chun-Chieh Chuang, Feng-Chi Hung, Jen-Cheng Liu
  • Patent number: 12721012
    Abstract: A display device is provided. The display device includes: a flexible screen body including a planar area and a bending area connected to the planar area; a color filter disposed on the flexible screen body and at least covering the planar area; a protective layer disposed on the flexible screen body and at least covering a part of the bending area; and a coverplate disposed on the color filter and at least covering the planar area. The protective layer and the coverplate are arranged at intervals.
    Type: Grant
    Filed: March 6, 2024
    Date of Patent: August 25, 2026
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Jing Zhou
  • Patent number: 12721025
    Abstract: Dispensers for dispensing solutions, such as solutions containing a crystallizable component and solvent(s), onto substrates in a controlled manner. In some embodiments, a dispenser of the present disclosure includes an elongated slot and corresponding slot opening that cooperate with a substrate so that a solution forms a meniscus between the dispenser and the substrate. The dispenser further includes a force-balancing reservoir containing wetting structures that interact with the solution to balance forces, for example, that would cause the solution to flow out of the slot when such flow is not desired. Methods of writing crystalline features, such as features of semiconductor devices, onto a substrate are also disclosed. In some embodiments, methods of the present disclosure involve strategically locating, on the substrate, regions that are either hydrophobic or hydrophilic to the relevant solution to define feature regions where the features will form.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: August 25, 2026
    Assignee: The University of Vermont and State Agricultural College
    Inventors: Randall L. Headrick, Richards Galt Miller, III
  • Patent number: 12721103
    Abstract: A semiconductor device includes: at least one power semiconductor die; a substrate having a first side and an opposite second side, the at least one power semiconductor die being arranged over the first side; an encapsulation encapsulating the at least one power semiconductor die; a pre-cured lamination layer covering the second side of the substrate, the pre-cured lamination layer being exposed from the encapsulation and configured to provide electrical insulation for the substrate after curing; and a detachable foil covering the pre-cured lamination layer, the detachable foil being configured to be removed from the pre-cured lamination layer.
    Type: Grant
    Filed: March 18, 2024
    Date of Patent: August 25, 2026
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerardo Pantoja