Abstract: The present disclosure provides a quantum dot light-emitting diode, a manufacturing method thereof, and a quantum dot film. The quantum dot light-emitting diode includes a first electrode, a second electrode, and a quantum dot light-emitting layer. The quantum dot light-emitting layer is disposed between the first electrode and the second electrode. The quantum dot light-emitting layer includes a first quantum dot and a second quantum dot, and an absolute value of a difference between a photoluminescence peak wavelength of the first quantum dot and a photoluminescence peak wavelength of the second quantum dot is less than or equal to 10 nm.

Abstract: Various embodiments of improved systems and methods are provided herein to monitor process chemicals used in a semiconductor process. More specifically, new semiconductor processing systems and methods that utilize infrared (IR) spectroscopy techniques are provided herein to monitor the composition and/or concentration of process chemicals utilized to process a substrate and/or the by-products produced during substrate processing. By monitoring the process chemicals and/or the by-products in real-time, the systems and methods described herein can be used to provide better process control and/or end-point detection for a wide variety of semiconductor processes.

Abstract: The present invention relates to an apparatus for bonding clips, a method of bonding clips, and a semiconductor package including semiconductor chips to which the clips are bonded using the method, and more particularly, to an apparatus for bonding clips, a method of bonding clips, and a semiconductor package including semiconductor chips to which the clips are bonded using the method, wherein the clips are sequentially bonded to the semiconductor chips by 1 unit so that a pitch difference between a lead frame array and a clip array is separately corrected to be the same and thereby, misalignment may be minimized so as to increase bonding accuracy of the clips to the semiconductor chips.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a first integrated circuit (IC) die stacked with a second IC die. The first IC die includes a plurality of photodetectors disposed within a first substrate. The second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate. The semiconductor capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a doped capacitor region. The first capacitor electrode overlies the second substrate and comprises a protrusion disposed in the second substrate. The capacitor dielectric layer is disposed between the first capacitor electrode and the second substrate. The doped capacitor region is disposed within the second substrate and underlies the first capacitor electrode. The plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.

Abstract: A display device is provided. The display device includes: a flexible screen body including a planar area and a bending area connected to the planar area; a color filter disposed on the flexible screen body and at least covering the planar area; a protective layer disposed on the flexible screen body and at least covering a part of the bending area; and a coverplate disposed on the color filter and at least covering the planar area. The protective layer and the coverplate are arranged at intervals.

Abstract: Dispensers for dispensing solutions, such as solutions containing a crystallizable component and solvent(s), onto substrates in a controlled manner. In some embodiments, a dispenser of the present disclosure includes an elongated slot and corresponding slot opening that cooperate with a substrate so that a solution forms a meniscus between the dispenser and the substrate. The dispenser further includes a force-balancing reservoir containing wetting structures that interact with the solution to balance forces, for example, that would cause the solution to flow out of the slot when such flow is not desired. Methods of writing crystalline features, such as features of semiconductor devices, onto a substrate are also disclosed. In some embodiments, methods of the present disclosure involve strategically locating, on the substrate, regions that are either hydrophobic or hydrophilic to the relevant solution to define feature regions where the features will form.

Abstract: A semiconductor device includes: at least one power semiconductor die; a substrate having a first side and an opposite second side, the at least one power semiconductor die being arranged over the first side; an encapsulation encapsulating the at least one power semiconductor die; a pre-cured lamination layer covering the second side of the substrate, the pre-cured lamination layer being exposed from the encapsulation and configured to provide electrical insulation for the substrate after curing; and a detachable foil covering the pre-cured lamination layer, the detachable foil being configured to be removed from the pre-cured lamination layer.

Abstract: In a method of manufacturing an electronic device, a substrate having a plurality of mounting regions on which first electronic components and second electronic components are mounted is provided, the substrate having a first surface and a second surface opposite the first surface. First electronic components are mounted on the first surface of the board via first bumps. At least one vapor shielding cover is positioned on the first surface of the substrate to cover at least one of the first electronic components. Second electronic components are mounted on the second surface of the substrate via second bumps. The second bumps are soldered with a vapor phase reflow process and during the vapor phase reflow process, the at least one vapor shielding cover is configured to prevent a heat transfer fluid in a vapor state from moving to the at least one first electronic component covered by the at least one vapor shielding cover.

Abstract: An example semiconductor memory device includes first and second active patterns, which are extended in a first direction and are disposed side by side in a second direction. Each of the first and second active patterns includes first and second edge portions, which are spaced apart from each other in the first direction. A pair of word lines are disposed to cross each of the first and second active patterns, a pair of bit lines are disposed on each of the first and second active patterns and are extended in a third direction, and a storage node contacts on the first edge portion of the first active pattern. When measured in the second direction, a first width of the storage node contact at a first level is larger than a second width at a second level. The first level is lower than the second level.

Abstract: Provided is a semiconductor circuit capable of protecting a semiconductor device that operates at a low voltage from a harmful pulse. A semiconductor circuit included in the semiconductor device has a semiconductor element 1 including: a first n-type semiconductor layer; a metal layer; and a Schottky barrier between the first n-type semiconductor layer and the metal layer, wherein the semiconductor element 1 is in forward connection between a signal line of the semiconductor device and a ground.

Abstract: An image sensor includes a substrate having a plurality of pixels. Each pixel includes a photoelectric conversion region and a floating diffusion region in the substrate, a pixel transistor including a pixel gate on the first surface of the substrate, a first transmission gate between the photoelectric conversion region and the floating diffusion region, extending into the substrate, and having a first width in a horizontal direction, and a second transmission gate between the photoelectric conversion region and the floating diffusion region, arranged between the pixel gate and the first transmission gate when viewed in a plan view, and having a second width less than the first width in the horizontal direction.

Abstract: A semiconductor package includes a photonic integrated circuit (PIC) die having a photonic layer, and an electronic integrated circuit (EIC) die bonded to the PIC die. The EIC die includes an optical region that allows the transmission of optical signals through the optical region towards the photonic layer, and a peripheral region outside of the optical region. The optical region includes optical concave/convex structures, a protection film and optically transparent material layers. The optical concave/convex structures are formed in the semiconductor structure. The protection film is conformally disposed over the optical concave/convex structures. The optically transparent material layers are disposed over the protection film and filling up the optical region. The peripheral region includes first bonding pads bonded to the photonic integrated circuit die, and via structures connected to the first bonding pads, wherein the protection film is laterally surrounding sidewalls of the via structures.

Abstract: A display device includes a substrate including a first display area and a second display area, a passivation layer overlapping the first display area and the second display area, an insulating layer overlapping the second display area and on the passivation layer, a first light emitting element on the passivation layer and in the first emission area; and a second light emitting element on the passivation layer and in the second emission area. The insulating layer includes a first surface facing the passivation layer, a second surface opposite to the first surface, and an inclined surface connecting the first surface and the second surface, the first light emitting element includes a first pixel electrode on the passivation layer, and the second light emitting element includes a second pixel electrode including a first portion on the passivation layer and a second portion on the inclined surface of the insulating layer.

Abstract: A layout method is provided. A timing analysis is performed based on design data of a standard cell to classify a plurality of device units of the standard cell into a timing-critical group and a non-timing-critical group. A plurality of first sources regions in the device units of the non-timing-critical group are aligned with a plurality of second sources regions in the device units of the timing-critical group in a first direction in floorplan of the standard cell in a layout. The device units of the timing-critical group are arranged in a first row of a cell array and the device units of the non-timing-critical group are arranged in a second row of the cell array. The first and second rows of the cell array share a common power line. First active regions of the first row are wider than second active regions of the second row.

Abstract: A silicon carbide wafer includes a substrate made of silicon carbide and an epitaxial layer made of silicon carbide and disposed on the substrate. A concentration of carbon vacancies in the substrate and the epitaxial layer continuously decreases from the substrate toward the epitaxial layer. The concentration of the carbon vacancies in the substrate is 3.0×1015 cm?3 or more.

Abstract: A fullerene derivative having a partial structure shown in the following General Formula (1) is provided. (in Formula (1), C*'s are adjacent carbon atoms that form a fullerene framework. Rf1 and Rf2 each independently represents a perfluoroalkyl group having 1 to 4 carbon atoms, and Rf1 and Rf2 may be linked to each other to form a ring structure).

Abstract: An overlay correction method for improving an overlay parameter of an ultra-high order component includes: obtaining misalignment components of an overlay through measurement; converting the misalignment components into overlay parameters; applying a conversion logic between the overlay parameters; converting the overlay parameters into aberration input data; and performing an exposure process by applying the aberration input data to an exposure machine, wherein the overlay parameters are divided into a first overlay parameter shifting in a first direction that is an extending direction of a slit, and a second overlay parameter shifting in a second direction that is perpendicular to the first direction, and the performing of the exposure process includes correcting the first and second overlay parameters including a higher-order component of a 3rd order or greater with respect to a location of the slit in the first direction.

Abstract: Display panels and array substrates are provided. The array substrate includes a first base, a first metal layer disposed on the first base and including scanning lines, a second metal layer disposed on the first metal layer and including data lines, a third metal layer disposed on the second metal layer and including pixel electrodes, and a fourth metal layer disposed between the third metal layer and the second metal layer. The fourth metal layer includes a transparent shielding electrode in which at least one repair hole is formed. An orthographic projection of the repair hole on the first base overlaps a part of an orthographic projection of at least one of the data lines and the scanning lines on the first base.

Abstract: An integrated circuit device includes a substrate having an active region, a word line extending in the substrate in a first horizontal direction, a bit line extending on the word line in a second horizontal direction, a bit line contact electrically connecting the bit line to the active region, a doping contact connecting the bit line contact to the active region, a cell pad having a horizontal width greater than that of the active region, a buried contact that digs into one side wall of the cell pad, and a conductive landing pad facing the bit line in the first horizontal direction. The doping contact includes a first doping contact and a second doping contact, and a thickness of the first doping contact in the vertical direction is less than that of the second doping contact in the vertical direction.

Abstract: A semiconductor chiplet device includes a first die, a second die, a decoupling circuit and an interposer. The interposer includes a plurality of power traces and a plurality of ground traces. The first die and the second die are arranged on a first side of the interposer according to a configuration direction, and are coupled to the power traces and the ground traces. The decoupling circuit is arranged on a second side of the interposer, and is coupled to the power traces and the ground traces. The power traces and the ground traces are staggered with each other, and an extending direction of the ground traces and the power traces is the same as the configuration direction.