Patents Examined by Anthony Ho
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Patent number: 11967529Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.Type: GrantFiled: November 10, 2020Date of Patent: April 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
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Patent number: 11966132Abstract: A display device includes signal lines, first driver terminals that are provided in a first peripheral region and to which a first driver IC can be coupled, second driver terminals to which a second driver IC can be coupled, a plurality of inspection terminals provided in the first peripheral region, first inspection switches coupled to the first driver terminals and configured to be capable of switching coupling and interruption of the inspection terminals and the signal lines, and second inspection switches coupled to the second driver terminals and configured to be capable of switching coupling and interruption of the inspection terminals and the signal lines.Type: GrantFiled: September 20, 2021Date of Patent: April 23, 2024Assignee: Japan Display Inc.Inventors: Keita Sasanuma, Kengo Shiragami, Naoyuki Obinata
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Patent number: 11968845Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a carbon nanotube structure, a source electrode and a drain electrode. The gate insulating layer is located on the gate electrode. The carbon nanotube structure is located on the gate insulating layer. The source electrode and the drain electrode are arranged at intervals and electrically connected to the carbon nanotube structure respectively. The thin film transistor further includes an interface charge layer, and the interface charge layer is located between the carbon nanotube structure and the gate insulating layer.Type: GrantFiled: January 17, 2022Date of Patent: April 23, 2024Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Gao-Tian Lu, Yang Wei, Shou-Shan Fan, Yue-Gang Zhang
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Patent number: 11957031Abstract: A display device is provided. The present disclosure allows a distance between a protective layer and a coverplate to be greater than or equal to a default value in an overlapping area of the protective layer and the coverplate, so the coverplate will not squeeze the protective layer, thereby preventing a risk of cracking the display device.Type: GrantFiled: May 31, 2021Date of Patent: April 9, 2024Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Jing Zhou
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Patent number: 11955460Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.Type: GrantFiled: October 5, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 11948930Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.Type: GrantFiled: November 13, 2020Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
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Patent number: 11950508Abstract: A light emitting device includes a first electrode, a second electrode, and at least one emission layer between the first electrode and the second electrode and includes at least one polycyclic compound represented by Formula 1 below, thereby exhibiting long service life characteristics. In Formula 1, the substituents are the same as defined in the detailed description.Type: GrantFiled: July 26, 2021Date of Patent: April 2, 2024Assignee: Samsung Display Co., Ltd.Inventors: Taeil Kim, Junha Park, Sun Young Pak, Jang Yeol Baek, Kyoung Sunwoo, Mun-Ki Sim, Chanseok Oh, Minjung Jung
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Patent number: 11942492Abstract: An image sensing device includes a semiconductor substrate, a photoelectric conversion region structured to generate charge carriers from incident light and capture the charge carriers using an electric potential difference caused by a demodulation control signal applied to the photoelectric conversion region, and a circuit region disposed adjacent to the photoelectric conversion region, the circuit region including a plurality of pixel transistors that generate and output a pixel signal corresponding to the charge carriers captured by the photoelectric conversion region. The circuit region includes a first well region formed to have a first length in a first direction, and a second well region formed below the first well region such that a lower end of the first well region is in contact with an upper end of the second well region, and formed to have a second length shorter than the first length in the first direction.Type: GrantFiled: August 13, 2021Date of Patent: March 26, 2024Assignee: SK HYNIX INC.Inventor: Jae Hyung Jang
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Patent number: 11942380Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.Type: GrantFiled: October 26, 2020Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
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Patent number: 11943993Abstract: The present invention relates to a process for producing a layer of a crystalline A/M/X material, which crystalline A/M/X material comprises a compound of formula [A]a[M]b[X]c, wherein: [M] comprises one or more first cations, which one or more first cations are metal or metalloid cations; [A] comprises one or more second cations; [X] comprises one or more halide anions; a is an integer from 1 to 6; b is an integer from 1 to 6; and c is an integer from 1 to 18, wherein the process comprises disposing on a substrate a precursor composition comprising: (a) a first precursor compound comprising a first cation (M), which first cation is a metal or metalloid cation; and (b) a solvent, and wherein the solvent comprises: (i) a non-polar organic solvent which is a hydrocarbon solvent, a chlorohydrocarbon solvent or an ether solvent; and (ii) a first organic amine comprising at least three carbon atoms. Also described are compositions useful in the process of the invention.Type: GrantFiled: October 18, 2019Date of Patent: March 26, 2024Assignee: OXFORD UNIVERSITY INNOVATION LIMITEDInventors: Henry James Snaith, Bernard Wenger, Pabitra Kumar Nayak, Nakita Kimberly Noel
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Patent number: 11935888Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.Type: GrantFiled: April 1, 2020Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pin-Dai Sue, Ting-Wei Chiang, Hui-Zhong Zhuang, Ya-Chi Chou, Chi-Yu Lu
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Patent number: 11935747Abstract: A method of manufacturing a semiconductor device includes depositing a photoresist material over a substrate. The substrate is rotated to spread the photoresist material. A gas is blown to an edge of the substrate when rotating the substrate. The rotating of the substrate is stopped. The blowing of the gas is stopped.Type: GrantFiled: June 30, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Hsin Liu, Ming-Jhih Kuo, Chun-Yen Tai
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Patent number: 11930656Abstract: A foldable display device assembly includes a rigid film having first and second sections spaced apart from each other, the rigid film being foldable about a folding axis disposed between the first and second sections of the rigid film; an adhesion structure having first and second adhesion sections spaced apart from each other, the first and second adhesion sections being disposed on the first and second sections of the rigid film, respectively; a lower flexible module disposed on the adhesion structure; a flexible display module disposed on the lower flexible module; and an upper flexible module disposed on the flexible display module.Type: GrantFiled: December 25, 2022Date of Patent: March 12, 2024Assignee: Samsung Display Co., Ltd.Inventor: Myoung Seo Park
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Patent number: 11929334Abstract: A method of making a semiconductor device involves the steps of disposing a first semiconductor die over a substrate and disposing a beam homogenizer over the first semiconductor die. A beam from the beam homogenizer impacts the first semiconductor die. The method further includes the steps of determining a positional offset of the beam relative to the first semiconductor die in a number of pixels, using a first calibration equation to convert the number of pixels into a distance in millimeters, and moving the beam homogenizer the distance in millimeters to align the beam and first semiconductor die.Type: GrantFiled: October 12, 2020Date of Patent: March 12, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: Wagno Alves Braganca, Jr., KyungOe Kim, TaeKeun Lee
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Patent number: 11930649Abstract: A transparent top electrode composite film for organic optoelectronic devices includes a substrate, an MoOx film layer coated on the substrate, a doped Ag-based film layer coated on the MoOx film layer and an HfOx film layer coated on the doped Ag-based film layer. A preparation method of the transparent top electrode composite film, which is achieved under vacuum and low temperature, includes steps of (A) depositing an MoOx film layer on a substrate through thermal evaporation process or electron beam evaporation process without heating the substrate; (B) depositing a doped Ag-based film layer on the MoOx film layer through sputtering process or evaporation process; and (C) depositing an HfOx film layer on the doped Ag-based film layer through reactive sputtering process, thereby obtaining the transparent top electrode composite film. The composite film is able to be used as a top electrode material for organic optoelectronic devices.Type: GrantFiled: December 30, 2021Date of Patent: March 12, 2024Assignee: University of Electronic Science and Technology of ChinaInventors: Deen Gu, Xin Zhou, Yadong Jiang, Mengru Chen
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Patent number: 11923213Abstract: Proposed is a substrate heating unit including: a laser generator providing a laser beam for heating a substrate; and a beam shaper processing the laser beam from the laser generator and selectively providing one of a first beam having a uniform energy distribution and a second beam having an edge-enhanced energy distribution to the substrate.Type: GrantFiled: December 20, 2020Date of Patent: March 5, 2024Assignee: SEMES CO., LTD.Inventors: Tae Shin Kim, Young Dae Chung, Ji Hoon Jeong, Jee Young Lee, Won Geun Kim
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Patent number: 11925077Abstract: A display apparatus includes: a display panel including a display area, and a pad area adjacent to the display area; and a circuit board attached to the pad area. The pad area includes at least one signal pad terminal electrically connected to a first signal line extending through the display area, and at least one dummy pad terminal spaced from the first signal line. The circuit board includes a signal lead terminal connected to the signal pad terminal, and a dummy lead terminal connected to the dummy pad terminal.Type: GrantFiled: March 18, 2019Date of Patent: March 5, 2024Assignee: Samsung Display Co., Ltd.Inventors: Byoung Yong Kim, Bong Hyun You
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Patent number: 11923461Abstract: A semiconductor device includes a drift layer, a channel layer, a source layer being the first conductivity type, a gate layer, a body layer, a shield layer and a drain layer. The channel is disposed on the drift layer. The source layer is disposed on a surface layer portion of the channel layer. The gate layer is arranged to be deeper than the source layer. The body layer is arranged to be deeper than the source layer. The shield layer is disposed at a portion of the channel layer between the gate layer and the drift layer. The shield layer is maintained at a potential different from a potential of the gate layer. The drain layer is disposed at a side opposite to the channel layer. A depth ratio of a depth of the gate layer to a depth of the body layer is equal to or larger than 0.45.Type: GrantFiled: June 18, 2021Date of Patent: March 5, 2024Assignee: DENSO CORPORATIONInventor: Kenji Kono
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Patent number: 11923479Abstract: A light-emitting element and an electronic apparatus capable of reducing the element area and realizing a stable electrical connection. A light-emitting element according to the present technology includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer laminated in this order, and a light-emitting surface, a non-light-emitting surface, and a side surface connecting the light-emitting surface and the non-light-emitting surface. The side surface is inclined. A first electrode is in a concave portion in the light-emitting surface at a periphery of the first semiconductor layer. A second electrode is on a non-light-emitting surface side of the laminate. A third electrode is on the non-light-emitting surface side of the laminate and is insulated from the second electrode. The side wiring electrically connects the first electrode and the third electrode via the side surface.Type: GrantFiled: August 7, 2019Date of Patent: March 5, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Nobuhiro Sugawara, Yasunari Hanzawa, Shinsuke Nozawa, Masaki Shiozaki, Takeshi Satou
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Patent number: 11923412Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.Type: GrantFiled: February 6, 2023Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Rishabh Mehandru, Stephen Cea, Anupama Bowonder, Juhyung Nam, Willy Rachmady