Abstract: A compiler system compiles a source program described with assembler instructions, each of which defines microoperations, into a target program for use in a digital signal processor. If two of the assembler instructions are interlocked with each other and if another assembler instructions which is not associated with the interlocked instructions is present, it is inserted between the interlocked instructions to thereby reorder the microoperations of the source program. Thereafter, the microoperations thus reordered are combined so as not to conflict with each other with regard to the fields of the assembler instructions and resources used by the assembler instructions. Prior to combining the microoperations, whether or not a basic block of assembler instructions included in the source program having a loop may be determined. If so, a head portion of the basic block forming the loop may then be transferred to a tail portion of the basic block forming the loop.

Abstract: A firmware state apparatus for controlling data transfer on multiple independent data lines between a telephone communications system and computer system. At least one processor having a program counter is employed for control data transfer. A processor memory is associated with the processor and has a plurality of firmware instructions divided into groups based upon the number of predefined states which are required for performing data transfer. Certain groups of instructions include test instructions for evaluating conditions related to the line to control sequencing to a next one of the predefined states. A shared memory has a plurality of locations for line table information for at least one line with at least one location containing a program counter address specifying a starting instruction of a corresponding one of the group of instructions to be executed by the processor.

Abstract: An apparatus and method for processing of interrupts in a computer system includes interrupts which are presented substantially simultaneously to each of a plurality of processors in the computer system. Each of the plurality of processors may respond to the interrupts and the first processor assigned to handle the interrupt prevents the other processors from handling the interrupts. The present invention further discloses means for disabling processors from responding to interrupts.

Abstract: A method accumulates the status of the execution of an arithmetic operation by an arithmetic processor having hardware elements for performing the steps of the operation, where each step is based on one or more operands and produces an intermediate or final result and possibly produces a corresponding status indicator. The method includes simulating the hardware elements in a model that performs simulated steps analogous to the steps performed by the hardware elements, each simulated step resulting in an intermediate or final status result; and while the arithmetic processor executes the arithmetic operation, applying each status indicator to the point in the model that corresponds to the point in the arithmetic processor where the result corresponding to the status indicator is applied, whereby the final result of the operation of the model will represent the accumulated status of the execution of the arithmetic operation.

Abstract: A computer system with provision for inserting/removing memory cartridges is improved by inhibiting erroneous operation as a result of noise produced on insertion/removal of a memory cartridge. Removable cartridges are connected/disconnected from a cartridge bus which is distinct from the system bus to which all other components are coupled. A controlled isolation is provided between the two buses. An idler routine ensures that in the absence of operator requested tasks the isolation prevents noise on the cartridge bus from reaching the system bus. When the processor executes an instruction (or only selected instructions) the isolation is disabled so that data/instructions can flow to/from the system and cartridge bus.

Abstract: An electronic equipment has a central processing unit (CPU), a first memory accessable by the CPU, a first setting circuit for holding a signal representative of a rated access time of the first memory and a removable auxiliary memory which includes a second memory accessable by the CPU and a second setting circuit for holding a signal representative of a rated access time of the second memory.

Abstract: The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configuration, it is possible to determine the logical address from the physical address that was output to an external circuit, without the microprocessor outputting the logical address directly to the external circuit.

Abstract: A data transfer driver transfers multiple byte data words supplied by a data processing device to a peripheral device as a sequence of single data bytes. The driver operates selectively in either a handshaking mode, wherein data bytes are transferred to the peripheral device asynchronously in response to handshaking signals from the peripheral device, or in a streaming mode where data bytes are transferred to the peripheral device periodically. The driver includes circuitry that permits the data processing device to check the operation of the driver and to monitor handshaking signals produced by the peripheral device.

Abstract: An instruction processor effecting operations for register operands and for processing branch instructions to perform address calculations for branch destination instructions, comprising general-purpose registers storing data including results of operations of said instruction processor, address adders calculating the address of branch destination instructions by using data read out from the general-purpose register and an ALU performing arithmetical or logical operations on the data read out from the general-purpose register in the decode cycle of the instructions. The result of the arithmetical or logical operation is inputted into the address adder but not from the general-purpose register, in the case where the result of the arithmetical or logical operation is utilized for address calculation in the execution of a succeeding instruction.

Abstract: A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.

Abstract: An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having a sequence control information and a data to be processed.

Abstract: A RAM buffer controller for managing the address input lines of a RAM buffer to simulate the operation of two FIFO's therein. Apparatus is included for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage "transmit and receive" FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Apparatus is also included for transmitting packets from said buffer organized into one or two linked lists. Further, apparatus is included for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor.

Abstract: A control element incorporated in an IC card divides externally input data into a plurality of words. It adds a word-discriminating data item and a chain data item to each of these words, and writes these words into the data memory incorporated in the IC card. Each chain data item indicates the storage location within the data memory where the word next to the word to which the chain data item has been added is stored. Each word-discriminating data item indicates whether or not the data with the word-discriminating data item added thereto is the first of the words forming the externally input data. The control element adds, to the first word, a word-discriminating data item whose most significant bit is "O", and adds a chain data item, whose value is also "O", to a word when the next word thereto is the last word.

Abstract: A memory node in a computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to the memory node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue.

Abstract: A method of monitoring signal lines on a computer data channel, and copying the respective data transmissions which occur in time sequence into a memory in space sequence corresponding to the time sequence, includes recognizing particular data channel signals, and includes displaying selected portions of the recorded tabulations of data transmissions, which portions include the data transmissions bounded about the recognized particular data transmission.

Abstract: A local-area-network based system for shared remote access or control of application programs in one or more computers by one or more other computers is provided having particular utility for trading rooms of securities firms, wherein each operator position is permitted the capability to access any of a number of information services. Information services, each of which communicates with a personal-computer-based video source running an applications program specific to that information service, are represented on a local-area network as nodes called servers. Each server runs the application program, unmodified, together with other terminate-and-stay-resident software which periodically broadcasts a video message, the content of which is the change of the application program display screen contents since the time of the last broadcast.

Abstract: Apparatus and method for storing magnetic tape format data separately stores the tape data from the tape-related information, such as file markers and interblock gap signals. The data and data-related signals are stored in separate finite length buffer memories, which when filled to a predetermined capacity are transferred to a write-once read-many (WORM) optical disk, and stored in contiguous locations beginning at one end of the addressable space on the optical disk. A separately generated tape record map list, including the WORM optical disk address of the aforementioned tape data and tape-related signals is created and stored on the optical disk in sequentially contiguous locations corresponding to sequential tape reel numbers beginning at the opposite end of the addressable space on the optical disk. The data thus recorded on the WORM optical disk is recoverable in the original magnetic tape format by recomposing the data stored in the WORM optical disk in the original magnetic tape data format.

Abstract: A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Abstract: In a computer system in which a storage unit is accessed by a host computer, protection key information for each of a plurality of areas of a storage volume, is stored into the storage volume mounted in the storage unit. When the storage volume is mounted on the storage unit, the storage unit reads out protection key information stored in the storage volume and stores it into a memory provided in the storage unit. When an access request for one of the plurality of areas of the storage volume is received from the host computer, the access request is collated with the protection key information stored in the memory relating to the requested area, and the access request is permitted or inhibited in accordance with the collating result.

Abstract: The creation of address spaces that need not map in their address range all of the routines of the operating system basic control program (BCP) is provided. The BCP, though, will have easy access to (addressability of) the home address space, i.e. to the virtually mapped and addressable control blocks therein. Addressability can be switched from a previously dispatched address space to the home address space. The dispatcher becomes capable of addressing the home address space when predetermined bits in a program status word are set. Once the home address space becomes addressable, the BCP is now capable of easily accessing control blocks in the home address space without the need to modify CPU status or pointers to any other address spaces. If pointers to any other address space are modified, current address translation in the home address space would not be affected. Providing access to the home address space increases performance and reduces complexity.