Abstract: A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30).

Abstract: A method is provided for optimizing performance in a fixed clock rate computer system. A control word is provided having a control portion for operational instructions and a programmable timing portion. The programmable timing portion includes a value representative of the sum of execution time and inter-execution delay time. A counter is provided for receiving the value representative of the execution and inter-execution times. The counter is capable of generating a signal to indicate an end of decrementing operation. The operational instructions are executed simultaneously with the processing of the time value in the counter so that a subsequent instruction is executed only when an end of operation signal is received from the counter.

Abstract: A document filing system is provided for storing a large amount of information in proper arrangement for facilitating utilization thereof by a user, while allowing semantical retrieval to be realized even from vague fragmental information. Further, a method is provided for expressing the facts consitituting information in terms of "concepts" representing things and "relations" defined between the concepts internally of computer, and a method of inputting user's information to a computer through dialogical procedure and retrieving desired information. Information stored of the computer architects internally a concept network which is displayed in various forms such as hierarchical form based on subsumption relations between the concepts, hierarchical representation based on part-whole relation between the concept, a frame display of a single concepts, and tabular representation of a set of concepts belonging to a given class.

Abstract: In a system based upon a microprocessor, the instruction set of which includes only one trap instruction, a software monitor is provided in which the user can define and monitor software break points without using trap instructions, thereby leaving the entire instruction set available to a user to execute, develop, or debug software containing trap instructions. To accomplish this result, software break points are defined at desired addresses by replacing user instructions at such addresses with call instructions that call a monitor routine which handles software break points. The argument of the call instruction is made equal to its op code. The portion of the monitor that handles software break points is entered at an address equal to the op code of the call instruction inserted at the break point address. This procedure avoids overwriting errors that otherwise would occur when software break points are defined at consecutive locations of the user program.

Abstract: In combination with a multiprocessing and multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new architecture for the execution of the call instruction, the return instruction, and the trap procedure is implemented partly in firmware and partly in hardware. The architecture includes a new stack mechanism for storing hardware managed control information in a control frame and software controlled data in a data frame.

Abstract: A memory access control system has a main memory having a plurality of memory banks divided into two groups, thus enabling parallel processing for data, a command/address bus line, a write data bus line, a read data bus line, and a device for simultaneously activating one request for access to the memory bank belonging to one group and another request for access to the memory bank belonging to the other group.

Abstract: The invention relates to the maintenance of integrity of transmitted messages within a data processing system. The system generates selective message identification indicia based upon the nature and content of the message, transmits the indicia with the message and selective regenerats the identification indicia at the point of message receipt for comparison with the transmitted indicia prior to release of the received message.

Abstract: A data transfer control unit comprises a first address register, a second address register and a control circuit. The first address register stores a first final address value of a memory area of a memory into which data is to be transferred. The second address register stores a second final address value of data which has already been transferred to the memory area of the memory. The control circuit compares the first final address value and a second final address value with an address value of data access by a CPU in order to generate a memory indication signal indicative of whether the address value of data accessed by the CPU belongs to the addresses of the data which has already been stored or has not yet been stored. The control circuit further prohibits a data transfer from the memory area to the CPU only when the address value of the data accessed by the CPU belongs to the addresses of the data which have not yet been stored in the memory.

Abstract: A packet-switching system having a buffer memory for storing received packets. The system has a FIFO-type table for storing data items each consisting of the start and end addresses of every region of the buffer memory from which data has been read out and transferred to a receiving station and which has thus become vacant. The start and end addresses of each region of the buffer memory are controlled, thereby achieving a high-speed control of the buffer memory.

Abstract: An input/output device monitors the transmission of information between a processor of a programmable controller and sensors and actuators of a process to be controlled. This device includes electronic circuits adapted for calculating the parities of the digital words which pass therethrough, these parities being compared with corresponding parities calculated by the processor which thereafter invalidates the words having two different parities.

Abstract: A computer based function control system is particularly suited for use as a software security device on the highly popular personal computers or a micro-processor driven function. The system includes an encrypted security message uniquely encoded at predetermined locations within the software or function program. The software or function program includes pre-set errors in it to cause failure of execution of the function or software program unless the errors are nulled during operation of the function or software program. A separate electronic key for retrieving, recognizing, decrypting, encrypting, and producing the null signals is connected to the communications port of the computer from which the key draws its power as well as the security message passed from the computer to the key and back to the computer. There is interchange of moving target and validation information between the computer software and the electronic key.

Abstract: A method and apparatus for simulating memory devices in a logic simulation machine include a finite state machine (FSM) having input/output (I/O) sources, instruction storage resources, a real memory resource, and instruction execution resources. A plurality of memory device ports to be simulated are defined and associated with corresponding respective subsets of the I/O resources of the FSM. Permutated sets of simulated memory array access signals, such as data, address, and control, are bound to selectable ones of the simulated memory ports and stored in the FSM, with the parameters of the memory operation established by the simulated signals. Stored sets of access instructions, representative of memory access operations, are augmented by the simulated signals and executed by the FSM against the real memory resource. All array instructions representing the same memory array share the same address space in the real memory resource.

Abstract: A digital processor has four components: a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.

Abstract: A microcomputer having an instruction memory is provided with a high-speed sense amplifier which can selectively operate in either of a high-speed operation mode or a low-speed operation mode. The high-speed sense amplifier is activated full time or at a large duty rate in the high-speed operation mode and is activated at a low-duty rate in the low-speed operation mode. By operating at a low-duty rate in the low-speed mode, a considerable power savings is realized while retaining the high speed benefits of the sense amplifier, which may be in the form of a current mirror-type sense amplifier or the like.

Abstract: A buffer memory is used to store data from the input/output device arrayed corresponding to the data rate of said input/output data device. A threshold is selected for beginnig an unload cycle of the buffer memory which will permit said buffer memory contents to be completely transferred at the higher channel data rate to the channel during the remaining time additional data is being accumulated in the memory. The threshold selection is adaptive such that subsequent data block lengths are utilized to calculate a new threshold maintaining data transfer rates from the input/output device into the channel at an optimum value.

Abstract: An asynchroonous interface device changes the serial data format of the video signal output of a computer intended for display on a cathode ray tube (CRT), to a video signal having parallel data format for a liquid crystal display (LCD). The device includes a read/write control circuit which responds to a clock signal corresponding to the synchronizing signal of the serial signal and to an asynchronous clock signal. Data signals which were removed from the serial signal and temporarily stored in memory are read out as parallel data signals at the next read cycle when read address counter is counted.

Abstract: An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having sequence control information and data to be processed. The architecture employed enables placement of both the general purpose processor and the single purpose processor on a single semiconductor chip, and also enables asynchronous, parallel operation of the two processors.

Abstract: An improved keyboard assembly is provided wherein a partition is positioned between adjacent keys and prevents an inadvertent simultaneous operation of two or more keys. The paartition can be advantageously utilized to control the cursor moving keys on a word processor keyboard thereby permitting the keys to be closely positioned adjacent each other while insuring only the desired key will be activated.

Abstract: An input/output control system includes an external data controller connected to a plurality of input/output units, a central processor, and a main storage accessible from the external data controller and the central processor. The main storage has a storage area corresponding to each input/ouptut unit and a storage area storing information to arrange a queue for a plurality of priority classes for determining the start priority of each input/output unit. At execution of a start instruction, the central processor sets a control information of the input/output unit to an associated storage area of the main storage and updates the queue arrangement information. The external data controller starts an input/output unit registered to a queue having the highest priority. The start operation is achieved according to the control information of the input/output unit stored in the main storage.

Abstract: A method for partitioning an original string of data elements into two substrings on a distributed processing system is disclosed. The elements are each of a first or a second type and the original string consists of a plurality of string fragments each composed of elements of only one type. The method operates to pass the identity of each fragment tail element to the head element of the next fragment, further from a true head element of the original string, composed of the same type elements as the tail element. The passed identities enable forming the two substrings from fragments of the same type elements.