Abstract: A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 1 megabyte address space to be selectively mapped to a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

Abstract: In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.

Abstract: A communications extension link for use between a computer and a keyboard and display unit has at the computer site a first interface circuit connected to it and adjacent to the keyboard and display unit a second interface circuit connected to it. The two interface circuits may then be spaced serveral hundred feet by an extension cable. The first interface circuit includes capacitors connected between keyboard data and clock lines and a positive supply terminal, and buffer amplifiers are placed in the signal lines relating to the display unit. The second interface circuit employs discrete resistors between clock and data lines and the positive supply terminal, and between the vertical sync line and logic ground. In addition, capacitance is added between the positive supply terminal and logic ground.

Abstract: A semiconductor memory controller chip associated with a remote DMA device, a multispeed microprocessor and a DRAM memory requiring refreshing periodically includes refresh circuits for generating refresh signals for controlling refreshing of the memory during transparent and contention refresh operations. When a conflict occurs between the DMA device requesting access to the memory and the occurrence of a transparent refresh operation, control signals are generated to allow the memory to be refreshed prior to the time the DMA device is given access to the memory, thereby eliminating the need for a contention refresh operation. Control signals are also generated in accordance with the speed of the microprocessor for synchronizing the operation of the microprocessor with the operation of the DMA device.

Abstract: In a multiprocessor system having a plurality of independent modules including a processor and a memory where the modules are connected via a common transmission path, a transmission control section for handling the interface with the transmission path between the modules is also equipped with a dedicated processor and controlled by its own microprogram. In accordance with the present invention, the memory for storing the microprogam therein is constituted by a writable memory, and the system is so configured that the microprogram may be loaded not only from the inside of the concerned module but also from another module through the common transmission path. Since the microprogram of the transmission control section can thus be loaded from two routes, the system can be configured or reconfigured with significant flexibility.

Abstract: The capacity of programmable controllers with a processor module and I/O modules connected in a single equipment rack is expanded by connecting an I/O expansion module in one of the positions normally occupied by a conventional I/O module. The I/O expansion module communicates with the processor module through the rack backplane and also communicates with other racks of I/O modules and with node I/O modules through a serial data channel. Data for I/O modules on the serial data channel are stored in a bulk storage area in the processor module to expand the effective size of an image table of I/O status data that is maintained by the processor module. The processor module is programmed to operate with a backplane controller in the I/O expansion module to transfer data in or out of the bulk storage area.

Abstract: A system for initializing a set of channel controllers in an information processing system reduces the time of initialization, the number of steps used in a microprogram, and necessary hardware. Address pointers of a plurality of control data areas relating to one of the channel controllers are utilized. Initialization data is sequentially read from a main memory of the information processing system. Address pointers of a channel controller are calculated by a predetermined procedure from the initialization data and a device number of the channel controller. The calculated address pointer is written into a local memory of the channel controller. Initialization is terminated upon reading an end of initilization data.

Abstract: Machine language instructions corresponding to sequence instructions that are stored in a first memory are stored at addresses of a second memory corresponding to operating codes of the sequence instructions, and a processing unit executes a sequence control by the instructions fetched from the second memory. A jump instruction with non-designated jump-to address is stored in the second memory. Following fetching of the jump instruction from the second memory, the processing unit fetches the sequence instruction to be next executed from the first memory, and the operation code of that sequence instruction is transferred to the processing unit as a jump-to address of the jump instruction.

Abstract: A microprocessor having a multi-stage pipeline structure, comprises: a status flip-flop having its output changing when the instruction code of a predetermined instruction is decoded in the microprocessor; a circuit for outputting the output of the status flip-flop in synchronism with the output timing of an address for the bus cycle period of the microprocessor; and a circuit for sequentially storing the information, which appears at the input/output terminals of the microprocessor, as time-series data outside of the microprocessor. The time-series data is edited by discriminating the bus cycle of the microprocessor belongs to the bus cycle following an instruction on or before the predetermined instruction for changing the output of the status flip-flop or the bus cycle following an instruction on or after the predetermined instruction, with reference to the information outputted from the status flip-flop inside of the microprocessor to the outside of the same.

Abstract: A method for writing tagged (partitioned and classified) records from a first log stream to multiple recovery streams and discarding same from said first stream at the termination of the unit of recovery in a transaction-oriented system to permit first log stream reuse.

Abstract: A sixteen bit microprocessor includes an emulation bit that is loaded into an instruction register with 8 bit op codes. If the emulation bit is a "1", the 16 bit microprocessor operates internally as a 6502 type eight bit microprocessor, thereby emulating a 6502 microprocessor. If the emulation bit is set to a "0", the 16 bit microprocessor executes an instruction set of which the 6502 instruction set is a subset to effectuate internal 16 bit operation.

Abstract: A document processing apparatus has a heading word dictionary, a heading extractor, a heading rule dictionary, a heading decision section, a document architecture rule dictionary and, a document architecture decision section, for deciding a logical document architecture. The apparatus further comprises a rule application decision section and a candidate selection indication section to allow the operator to select any desired document architecture, when the document architecture decision section decides plural document architecture candidates exist in accordance with document architecture rules, thus improving the operability of the system. Further, the past rule application record information (priority order) is stored and updated so as to provide a learning function for providing better operability.

Abstract: A programmable logic device has a high level counter element and a programmable AND array suitable for control applications. Moore and Mealy state machines are readily implemented by the controller by virtue of its programmable AND array and counter which allow the next-state and output to be based on the contents of the counter as well as any set of input signals. Conditional testing can be made entirely state dependent, partially-state dependent, or state-independent. Multiway branching is also readily implemented since the presence of the programmable AND array allows the user to specify a number of sets of input conditions, so that from a given state, as determined by the counter contents, each set of input condition gives rise to a transition to a specified next state. Instructions can be stored in the AND array in a logical form directly useable by the hardware.

Abstract: A parallel processing search system for searching and updating a database at the request of a host system, including a master processor connected to a host system bus for transfer of information between said master processor and the host system bus; a data bus connected to the master processor; plural slave processors connected to the data bus for independently processing search respective requests under the control of the master processor; a disk drive interface adapted to be connected to a disk which stores a database; and a buffer memory connected to the data bus and the disk drive for storing the database retrieved from the disk and for sequentially placing data from the database on the data bus for match comparison by the slave processors so that a search of the database can be made by the slave processors under the control of the master processor.

Abstract: A virtual cathode ray tube device is used in a video graphics system having a source of data and a visual display device. This virtual CRT device includes a plurality of buffers, a plurality of VDRAMs, each of said VDRAMs having an internal shift register, a plurality of external shift registers, first apparatus for transferring data from said source of data to said buffers, second apparatus for transferring data from said buffers to said VDRAMs, third apparatus for transferring data from each of said VDRAMs to its internal shift register, and a fourth apparatus for transferring data from said internal shift registers to said plurality of external shift registers at a first rate. A fifth apparatus transfers data from said plurality of external shift registers to said visual display device at a second rate, said second rate being greater than said first rate.

Abstract: The information inspection system for data-processing equipment for the obtaining of electric signals representing auditory, visual and/or tactile information for vision-impaired typists has an interface which "listens-in" in the data bus of an electronic computer or an automated typewriter and thus scans the transmitted data practically without power and without affecting the operation of the data-processing equipment, and feeds same to the end device for the vision-impaired where they are presented in visual, auditory and/or tactile form. No special modification of the hardware and/or software of the data-processing equipment, and therefore of the automated typewriter or the electronic computer, is necessary.

Abstract: In a data processing system that stores a first and second version of a given data set, a method for synchronizing the first and second versions comprises steps of maintaining a sync-complete control field and a sync-in-progress control field in the inode of each of the first and second versions. Write accesses to the versions are modified so that the sync-complete control field and the sync-in-progress control field are cleared in response to any change in the associated version. The sync-complete control bits for the first and second versions are tested, and if either or both are cleared, then the sync-in-progress control field associated with a select source version is set. Next, a copy of the source version is transferred to a temporary file.

Abstract: A priority processor (1) and a non-priority processor (20) cooperatively access a common memory (30) by means of an address multiplexer (40) which memory and multiplexer are controlled by a control unit (60). The priority processor issues data strobe (DSSN), clock (CLK) and write control (WSN) signals to the control unit to which the non-polarity processor also issues various memory access request signals. By forming a preparation signal (DSSN=0), the priority processor, through the control unit, claims the memory for a memory access cycle if a prior memory access request by the non-priority processor occurred less than about a clock cycle earlier.

Abstract: A circuit providing a joystick interface to a computer. The circuit plugs into the cartridge slot of the computer and receives power from the computer. The circuit includes an analog interface circuit, a read only memory (ROM) containing both a machine language program to drive the analog interface circuit, and a machine language application program. The analog interface circuit includes an analog-to-digital converter, a clock circuit, and a decoder. The circuit of the present invention also includes a tri-state bus interface circuit to communicate the state of input switches to the computer.

Abstract: A data processor which specifies either of a predetermined maximum length of an adddress (a bits) and a length of an address less than the former length and at plural registers having a number of length of bits (r bits) of the maximum address length or greater. The data processor reads out lower-order d bits for data or r bits for an address of the one of the plural registers (7) specified by a first instruction to perform an arithmetic or logic operation, and writes the result into one of the plural registers. Moreover, the processor reads out bits having specified length of an address from the one of the plural registers specified in a second instruction to generate an a-bit address, and reads out d for data or r bits for an address from a main storage device (5) in response to the thus-generated address to write the d or r bits into one of the plural registers.