Abstract: Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.

Abstract: A method is provided for transforming a high-level language representation of a tensor computation graph into a low level language. The method includes assigning a tensor shape and a loop primitive. The method also includes generating, from the tensor computation graph and the assigned loop primitives, an initial loop structure. The method further includes positioning the layers of the tensor computation graph within a nested loop structure to provide a final loop structure, collapsing loops in the final loop structure, and mapping the collapsed loops to hardware components configured to execute the collapsed loops. The method can be applied to artificial intelligence (AI) and machine learning (ML) use cases for improved optimization of neural networks including compilation optimization for improving performance of simulations such as medical simulations, healthcare simulations, weather simulations, and/or simulations related to other complex systems, which can also support decision making.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: A filter manufacturing method and a filter manufactured by the filter manufacturing method are disclosed. The filter manufacturing method includes designating a use mode in a resonator to a first resonance mode, in response to designating to the first resonance mode, setting a band selected from a designated first frequency band to a passband in the resonator, switching the use mode in the resonator from the first resonance mode to a second resonator mode, in response to switching to the second resonance mode, setting a band selected from the first frequency band except for the passband to a stopband in the resonator, and manufacturing a primary filter including the resonator to which the passband and the stopband are set.

Abstract: Described herein are techniques for routing conductive wires in a wireless power transfer pad. Such techniques may comprise routing, for a length of wiring between a power source and an inductive coil, a first conductive wire configured to carry a first current, routing, for a first portion of the length of wiring, a second conductive wire next to the first conductive wire, wherein the second conductive wire is configured to carry a second current having a direction that is substantially opposite that of the first current, and routing, for a second portion of the length of wiring, a portion of the inductive coil next to the first conductive wire, wherein the portion of the inductive coil is configured to carry a third current having a direction that is substantially opposite that of the first current.

Abstract: A method, system, and computer program product are disclosed for implementing enhanced noise impact on function (NIOF) analysis of an IC design having nets in multiple different variable voltage domains next to each other and modeling all multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. The NIOF analysis enables accurately identifying incorrect victim switching or functional fails, effectively and efficiently providing design verification and the ability to sign-off an IC design with a single run, and enable modifying an integrated circuit design to fix NIOF failures, and fabricating an integrated circuit.

Abstract: A wireless charging apparatus includes a receive end coil, a switch selection circuit, a plurality of charging circuits, and a receive end controller. An input end of the switch selection circuit is connected to an output end of the receive end coil, and an output end of the switch selection circuit is connected to an input end of each of the charging circuits.

Abstract: The present disclosure relates to reducing power consumption of test point circuit elements of an integrated circuit (IC) design. An ungated input clock for at least one testing point circuit element for the IC design can be identified. The IC design can be updated by coupling a test point clock gating circuit element to a clock gate input node of the IC design that is to receive the ungated input clock, to the at least one test point circuit element, and to a test mode signal generation element that is to provide a test mode signal to create an updated IC design. The test point clock gating circuit element can be enabled and disabled based on a logical value of the test mode signal to control a supply of the ungated input clock to the at least one testing point circuit element.

Abstract: Disclosed is an AI-based automated circuit generation method. The method includes obtaining design metrics; capturing a dependency relationship among design metrics by using an attention mechanism, extracting features by using a multi-layer Transformer structure to obtain an overall structure and a high-level feature representation of a circuit, and matching the high-level feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain a current circuit netlist; simulating the current circuit netlist to obtain a simulation report, and extracting error information from the simulation report; and correcting the current circuit netlist based on the error information, simulating a corrected circuit netlist again, looping until there are no errors in the simulation report, and outputting a final circuit netlist.

Abstract: A circuit includes a reference node having a reference voltage level, a first node that carries an input signal having a first voltage level or the reference voltage level, a second node that carries a power supply voltage, a voltage regulator including a source follower that outputs a gate signal having a fractional value of the input signal, a first control circuit that selects the higher of the power supply voltage or the gate signal as a first control signal, a second control circuit that selects the higher of the input signal or the first control signal as a second control signal, and first and second transistors coupled in series between the first node and the reference node and configured to receive the first and second control signals.

Abstract: A battery control device controls a battery system including a plurality of battery cells connected in series and a bypass circuit that bypasses each of the battery cells. Discharge is performed from each of the battery cells until remaining quantity of the battery cell decreases to a predetermined value. When the remaining quantity of the battery cell is decreased to the predetermined value, each of the battery cells is bypassed by the bypass circuit. When the remaining quantity of all of the plurality of battery cells is decreased to the predetermined value, discharge is performed from all of the plurality of battery cells.

Abstract: Systems and methods for implementing a quantum code using cat qubits as data qubits and transmon qubits as ancilla qubits is disclosed. In some embodiments, a three-level transmon is used and Chi-matching is performed to determine dispersive coupling coefficients between the cat qubits and first and second excited states of the transmon qubits, wherein the dispersive coupling coefficients are used to perform gates between the cat data qubits and the transmon ancilla qubits. The Chi-matching determines the dispersive coupling coefficients such that the cat qubits are rotated in a same manner while performing the gates regardless as to whether a given transmon ancilla qubit remains in a second excited state or has decayed to a first excited state.

Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes receiving an integrated circuit layout, inserting, into the integrated circuit layout, a design containing a first set of Front-End Of Line (FEOL) shapes of an integrated circuit and a first set of Back-End Of Line (BEOL) shapes of the integrated circuit, inserting, into the integrated circuit layout, a set of cells containing a second set of FEOL shapes of the integrated circuit and a second set of BEOL shapes of the integrated circuit, removing a subset of the second set of BEOL shapes that conflict with the design, and providing the integrated circuit layout that includes the design and the set of cells for fabrication of the integrated circuit. The second set of FEOL shapes includes contact shapes that define contacts of the integrated circuit.

Abstract: A method performed by battery charger configured to charge a vehicle battery, the method comprising charging the vehicle battery until a first measured voltage over the battery exceeds a first voltage threshold, halting charging for a third time period, measuring a second voltage over the battery at the end of the third time period, determining a battery type using a differential voltage, by calculating a difference of the first voltage threshold and the second voltage, and a set of predetermined conditions, wherein the predetermined conditions comprise: battery ? type = { U diff > U Pb ? lead - acid ? battery ? type U diff < U Li ? lithium ? battery ? type U Pb > U diff < U Li ? unknown ? battery ? type

Abstract: Cover properties are extended in formal verification to reach an effective end-of-test stage for a design under test. A formal verification task for a design under test may be received at a verification system. A cover property asserted in the formal verification task may be identified. An additional condition may be implemented for the identified cover property to extend the identified cover property to cause performance of the formal verification task to generate a trace to reach an effective end-of-test stage for the design under test in the event of a failure of the cover property.

Abstract: An integrated circuit includes a first power rail, a first signal line, a first transistor and a second transistor. The first power rail is on a back-side of a substrate and is configured to supply a first supply voltage. The first signal line is on the back-side of the substrate and is separated from the first power rail. The first transistor has a first active region is in a front-side of the substrate. The first active region is overlapped by the first power rail and is electrically coupled to the first power rail. The second transistor has a second active region that is in the front-side of the substrate. The second active region is separated from the first active region, is overlapped by the first signal line, and is configured to receive the first supply voltage of the first power rail through the first active region of the first transistor.

Abstract: A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Abstract: A system and method for routing Field Programmable Gate Arrays (FPGAs) includes an input device for acquiring a netlist with defined source, sink, and intermediate nodes, and processing circuitry that features a design router. The router leverages a negotiated-congestion routing component, which promotes the shared use and negotiation for intermediate nodes. The negotiation process employs a congestion cost based on several factors, including base, historical, and present usage costs, alongside node capacity. This system is characterized by a historical cost function focused on the base cost of nodes, favoring the use of those with costs below a specified threshold. A display device incorporated within the system allows for the continuous monitoring of the routing procedure and the efficiency of resource usage. The technology aims to streamline FPGA design by optimizing signal routing for performance and area efficiency.

Abstract: Fabrication of an electronic circuit is facilitated by providing a computer tool to enhance design of the electronic circuit to meet a design criteria. The computer tool facilitates obtaining one or more hybrid logical entities, where a hybrid logical entity includes a pull-up circuit and a pull-down circuit formed of transistors with different transistor types for pull-up versus pull-down, and different voltage thresholds for pull-up versus pull-down. Further, the facilitating includes incorporating the hybrid logical entity into the electronic circuit design to produce a revised electronic circuit design. The method further includes initiating manufacture of the electronic circuit pursuant, at least in part, to the revised electronic circuit design.

Abstract: A battery pack includes a casing, a cell group, a bracket, cell connection pieces, and output terminals. A plane where the output terminals of the battery pack are located is defined as an upper plane, a plane where the output terminals of the cell group are located is defined as a front plane, and a plane perpendicular to the upper plane and the front plane is defined as a side plane. One of the cell connection pieces includes a bracket-fixed surface, a cell connection surface, and a power supply output surface. The bracket-fixed surface is fixed on the bracket and parallel to the side plane. The cell connection surface is connected to the power supply output terminals of the cell group and parallel to the front plane. The power supply output surface is connected to the output terminals and parallel to the upper plane.