Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.

Abstract: Methods and systems for verifying a property of an integrated circuit hardware design. The method includes formally verifying, using a formal verification tool, that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time.

Abstract: Hybrid quantum-classical approaches for solving computational problems in which results from a quantum processor are combined with an exact method executed on a classical processor are described. Quantum processors can generate candidate solutions to a combinatorial optimization problem, but since quantum processors can be probabilistic, they are unable to certify that a solution is an optimal solution. A hybrid quantum-classical exact solver addresses this problem by combining outputs from a quantum annealing processor with a classical exact algorithm that is modified to exploit properties of the quantum computation. The exact method executed on a classical processor can be a Branch and Bound algorithm. A Branch and Bound algorithm can be modified to exploit properties of quantum computation including a) the sampling of multiple low-energy solutions by a quantum processor, and b) the embedding of solutions in a regular structure such as a native hardware graph of a quantum processor.

Abstract: This disclosure describes a quantum noise process analysis method, device, and storage medium, in the field of quantum processing technologies. The method may include performing quantum process tomography (QPT) on a quantum noise process of a target quantum system, to obtain dynamical maps of the quantum noise process, wherein the QPT involves at least one measurement of the target quantum. The method further includes extracting transfer tensor maps (TTMs) of the quantum noise process from the dynamical maps; and analyzing the quantum noise process according to the TTMs. The TTM is used for representing a dynamical evolution of the quantum noise process to reflect the law of evolution of the dynamical maps of the quantum noise process over time.

Abstract: For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.

Abstract: Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell is selected from a library to resize the initial driver cell and is used to replace the initial driver cell in the net. The alternative driver is selected such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the initial driver cell by no more than the capacitance increase margin.

Abstract: Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library.

Abstract: Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state.

Abstract: This disclosure provides a method to realize a hardware device, in particular a hardware device configured on a FPGA or manufactured as an ASIC, configured to meet maximum performances achievable by a certain algorithm defined by a high-level software code. The method is based on the steps of translating of the high-level software code into a corresponding low-level software code defining low-level operation, for executing the same operations defined by the high-level software code; then on estimating of certain parameters to calculate a peak performance value P and memory transfer performance Pm of the hardware device; finally, on realizing the hardware device with hardware resources having performance within the peak performance value P and memory transfer performance Pm.

Abstract: Disclosed is an improved approach for efficiently implementing a three-dimensional integrated circuit (3D-IC) design with heterogeneous and/or homogeneous dies. A first die design and a second die design in a three-dimensional (3D) electronic design maybe identified, and a wrapper design may be generated for at least a block of circuit component designs in the second die design for concurrent implementation of both the first and the second die designs. Both the first and the second dies of the 3D electronic design are concurrently implemented based at least upon a floorplan that is generated with at least the wrapper design for the 3D electronic design. A first wrapper and a second wrapper may be respectively generated for the first die design and the second die design based at least in part upon a result of the concurrent implementation.

Abstract: Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop

Abstract: A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.

Abstract: A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.

Abstract: An integrated circuit includes a first power rail, a first signal line, a first transistor and a second transistor. The first power rail is on a back-side of a substrate and is configured to supply a first supply voltage. The first signal line is on the back-side of the substrate and is separated from the first power rail. The first transistor has a first active region in a front-side of the substrate. The first active region is overlapped by the first power rail and is electrically coupled to the first power rail. The second transistor has a second active region that is in the front-side of the substrate. The second active region is separated from the first active region, is overlapped by the first signal line, and is configured to receive the first supply voltage of the first power rail through the first active region of the first transistor.

Abstract: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

Abstract: Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.

Abstract: Methods for modifying power use of a semiconductor device include receiving, at one or more processors, an activity stream of a simulation of a semiconductor device, the activity stream comprising a stream of signals. Using the one or more processors, integrated circuit actions are recognized from the activity stream, each integrated circuit action representing an abstraction of work done by the semiconductor device. The processor(s) determine one or more values associated with the integrated circuit actions. A model of power use is generated for the semiconductor device, the model based at least in part on the recognized integrated circuit actions and the associated values. Based on an output of the model, power use of the semiconductor device is modified. Other methods and systems related to determining, modeling, and predicting power/energy use of semiconductor devices are also disclosed.

Abstract: Correction method of mask layout and mask containing corrected layout are provided. The method includes providing a target layout including a plurality of main patterns. Each main pattern includes a first side and an opposite second side. Extending directions of the first side and the second side are perpendicular to a first direction. Each main pattern also includes a third side and an opposite fourth side. Extension directions of the third side and the fourth side are perpendicular to a second direction. The second direction and the first direction are perpendicular to each other. The method also includes acquiring position information of each main pattern, and obtaining position information of auxiliary patterns adjacent to each main pattern. The method also includes, according to the position information of the auxiliary patterns adjacent to each main pattern, arranging the auxiliary patterns adjacent to each main pattern around each main pattern.