Abstract: A method performed by battery charger configured to charge a vehicle battery, the method comprising charging the vehicle battery until a first measured voltage over the battery exceeds a first voltage threshold, halting charging for a third time period, measuring a second voltage over the battery at the end of the third time period, determining a battery type using a differential voltage, by calculating a difference of the first voltage threshold and the second voltage, and a set of predetermined conditions, wherein the predetermined conditions comprise: battery ? type = { U diff > U Pb ? lead - acid ? battery ? type U diff < U Li ? lithium ? battery ? type U Pb > U diff < U Li ? unknown ? battery ? type

Abstract: Cover properties are extended in formal verification to reach an effective end-of-test stage for a design under test. A formal verification task for a design under test may be received at a verification system. A cover property asserted in the formal verification task may be identified. An additional condition may be implemented for the identified cover property to extend the identified cover property to cause performance of the formal verification task to generate a trace to reach an effective end-of-test stage for the design under test in the event of a failure of the cover property.

Abstract: An integrated circuit includes a first power rail, a first signal line, a first transistor and a second transistor. The first power rail is on a back-side of a substrate and is configured to supply a first supply voltage. The first signal line is on the back-side of the substrate and is separated from the first power rail. The first transistor has a first active region is in a front-side of the substrate. The first active region is overlapped by the first power rail and is electrically coupled to the first power rail. The second transistor has a second active region that is in the front-side of the substrate. The second active region is separated from the first active region, is overlapped by the first signal line, and is configured to receive the first supply voltage of the first power rail through the first active region of the first transistor.

Abstract: A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Abstract: A system and method for routing Field Programmable Gate Arrays (FPGAs) includes an input device for acquiring a netlist with defined source, sink, and intermediate nodes, and processing circuitry that features a design router. The router leverages a negotiated-congestion routing component, which promotes the shared use and negotiation for intermediate nodes. The negotiation process employs a congestion cost based on several factors, including base, historical, and present usage costs, alongside node capacity. This system is characterized by a historical cost function focused on the base cost of nodes, favoring the use of those with costs below a specified threshold. A display device incorporated within the system allows for the continuous monitoring of the routing procedure and the efficiency of resource usage. The technology aims to streamline FPGA design by optimizing signal routing for performance and area efficiency.

Abstract: Fabrication of an electronic circuit is facilitated by providing a computer tool to enhance design of the electronic circuit to meet a design criteria. The computer tool facilitates obtaining one or more hybrid logical entities, where a hybrid logical entity includes a pull-up circuit and a pull-down circuit formed of transistors with different transistor types for pull-up versus pull-down, and different voltage thresholds for pull-up versus pull-down. Further, the facilitating includes incorporating the hybrid logical entity into the electronic circuit design to produce a revised electronic circuit design. The method further includes initiating manufacture of the electronic circuit pursuant, at least in part, to the revised electronic circuit design.

Abstract: A battery pack includes a casing, a cell group, a bracket, cell connection pieces, and output terminals. A plane where the output terminals of the battery pack are located is defined as an upper plane, a plane where the output terminals of the cell group are located is defined as a front plane, and a plane perpendicular to the upper plane and the front plane is defined as a side plane. One of the cell connection pieces includes a bracket-fixed surface, a cell connection surface, and a power supply output surface. The bracket-fixed surface is fixed on the bracket and parallel to the side plane. The cell connection surface is connected to the power supply output terminals of the cell group and parallel to the front plane. The power supply output surface is connected to the output terminals and parallel to the upper plane.

Abstract: Systems, computer-implemented methods and/or computer program products are provided for operating a quantum circuit on a set of qubits. According to an embodiment, a system can facilitate control of data transfer between two or more nodes. The system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a compilation component that compiles one or more communication paths between two or more nodes for transfer of yet-undetermined data along the one or more compiled communication paths. Alternatively and/or additionally, the computer executable components can comprise an interval boundary implementation component that can commonly set and trigger a successively repeating time point at two or more nodes to align performance at the two or more nodes of one or more quantum gate operations.

Abstract: An insulation resistance detection system for an electric vehicle is used to detect a positive insulation resistance between a positive electrode of a battery of the electric vehicle and an equipment grounding point, and detect a negative insulation resistance between a negative electrode of the battery and the equipment grounding point. The insulation resistance detection system includes a negative detection circuit, a positive detection circuit, and a control unit. The control unit controls the negative detection circuit to be charged to generate a first capacitor voltage, and controls the positive detection circuit to be charged to generate a second capacitor voltage. The control unit determines whether the negative insulation resistance is abnormal according to the first capacitor voltage and a battery voltage of the battery, and determines whether the positive insulation resistance is abnormal according to the second capacitor voltage and the battery voltage.

Abstract: A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Abstract: A method for process control using predictive long short term memory includes obtaining historical post-process measurements taken on prior products of the manufacturing process; obtaining historical in-process measurements taken on prior workpieces during the manufacturing process; training a neural network to predict each of the historical post-process measurements, in response to the corresponding historical in-process measurements and preceding historical post-process measurements; obtaining present in-process measurements on a present workpiece during the manufacturing process; predicting a future post-process measurement for the present workpiece, by providing the present in-process measurements and the historical post-process measurements as inputs to the neural network; and adjusting at least one controllable variable of the manufacturing process in response to the prediction of the future post-process measurement.

Abstract: A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to predict the timing of a fully optimized netlist. The reduced synthesis process has faster execution time compared to the optimized digital implementation synthesis process but results in comparable performance, power and area that is within a threshold of the results generated using optimized digital implementation synthesis process.

Abstract: Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated.

Abstract: This disclosure describes a quantum noise process analysis method, device, and storage medium, in the field of quantum processing technologies. The method may include performing quantum process tomography (QPT) on a quantum noise process of a target quantum system, to obtain dynamical maps of the quantum noise process, wherein the QPT involves at least one measurement of the target quantum. The method further includes extracting transfer tensor maps (TTMs) of the quantum noise process from the dynamical maps; and analyzing the quantum noise process according to the TTMs. The TTM is used for representing a dynamical evolution of the quantum noise process to reflect the law of evolution of the dynamical maps of the quantum noise process over time.

Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

Abstract: A power feeding control device controls a power feeding system including a plurality of battery cells feeding power to a load, a bypass lines which connects or disconnects each of the battery cells and the load, an external power feeding unit which is connected in parallel with the load and feeds power to the load. Before the bypass line starts switching of a connection state between each of the battery cells and the load, supply voltage from the external power feeding unit to the load is increased. Further, after the bypass line switches the connection state between each of the battery cells and the load, the supply voltage from the external power feeding unit to the load is decreased.

Abstract: An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test sequences.

Abstract: Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Abstract: Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs.