Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

Abstract: A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.

Abstract: A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

Abstract: An electrical device comprising a reconfigurable integrated circuit that includes paired top electrodes and bottom electrodes separated from each other by an active layer.

Abstract: Examples provide a method of virtualizing a hardware accelerator in a virtualized computing system. The virtualized computing system includes a hypervisor supporting execution of a plurality of virtual machines (VMs). The method includes: receiving a plurality of sub-programs at a compiler in the hypervisor from a plurality of compilers in the respective plurality of VMs, each of the sub-programs including a hardware-description language (HDL) description; combining, at the compiler in the hypervisor, the plurality of sub-programs into a monolithic program; generating, by the compiler in the hypervisor, a circuit implementation for the monolithic program, the circuit implementation including a plurality of sub-circuits for the respective plurality of sub-programs; and loading, by the compiler in the hypervisor, the circuit implementation to a programmable device of the hardware accelerator.

Abstract: Variation-aware delay fault testing suitable for carbon nanotube field-effect transistor circuits can be accomplished using an electronic design automation tool that performs long path selection by generating random variation scenarios, wherein a random variation scenario (RVS) is an instance of an input netlist where values for a set of process parameters for each gate are chosen from a set of values for each process parameter of the set of process parameters for that gate, the set of values being sampled from a distribution of that particular process parameter for that gate and includes a nominal value for that particular process parameter; calculating a total delay through a path for each RVS; and selecting at least two paths having highest total delays for each fault site under random variations of the RVSs. Delay test patterns can then be generated for the selected paths.

Abstract: A power supply device is provided with a disconnection means (AND element) for forcibly disconnecting a battery module from a series connection regardless of a gate signal. The power supply device forcibly disconnects partial battery modules from the series connection by the disconnection means (AND element) during powering by a power supply output, thereby performing control so that the accumulated discharge current amounts thereof per unit time become smaller than those of the other battery modules.

Abstract: Systems, machine readable media and methods are described for analyzing one or more physical systems using techniques that recognize patterns in underlying data and use the patterns to efficiently compute outputs using the patterns to reduce computations. The physical systems can be simulated with an estimation (e.g., an estimated power versus time waveform) that can be efficiently computed and then the estimation can be analyzed to detect patterns in the data. The detected patterns can each be analyzed with, in one embodiment, higher accuracy than the estimation to provide data that can be combined across multiple instances of each pattern to provide a higher accuracy evaluation of the system with a lower computational overhead.

Abstract: Methods and systems for verifying a hardware design for a multi-stage component is stall independent. The multi-stage component is configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled by a set of one or more enable signals.

Abstract: A method including: computing a value of a first variable of a pattern of, or for, a substrate processed by a patterning process by combining a fingerprint of the first variable on the substrate and a certain value of the first variable; and determining a value of a second variable of the pattern based at least in part on the computed value of the first variable.

Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.

Abstract: A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.

Abstract: A method for adaptive error correction in quantum computing includes executing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In an embodiment, the method includes estimating, responsive to determining an initial state of the quantum processor, a runtime duration for a quantum circuit design corresponding to a quantum algorithm, the quantum processor configured to execute the quantum circuit design. In an embodiment, the method includes computing an error scenario for the quantum circuit design. In an embodiment, the method includes selecting, using the error scenario and the initial state of the quantum processor, a quantum error correction approach for the quantum circuit design. In an embodiment, the method includes transforming the quantum algorithm into the quantum circuit design, the quantum circuit design including a set of quantum logic gates.

Abstract: A computer-implemented method for designing a floorplan for an integrated circuit includes determining a circuit design for the integrated circuit, wherein the circuit design for the integrated circuit has a system device and a logic device. Logical definitions for the system device and the logic device are determined. A plurality of interconnect devices are determined. A plurality of interconnect figures of merit (FOMs) associated with the plurality of interconnect devices are also determined. The method includes determining, with an optimization operation, a candidate floorplan for the circuit design based upon the logical definitions for the system device, the logic device, the plurality of interconnect devices, and the interconnect FOMs for the interconnect devices. The candidate floorplan is determined based upon parameters associated with computational performance, power consumption, and physical area of the candidate floorplan for the circuit design.

Abstract: An integrated circuit (IC) test engine extracts an input to output propagation delay for each cell instance of each of a plurality of cell types in an IC design from an SDF file for the IC design. The IC test engine extracts a node slack of each cell instance of each of the plurality of cell types of the IC design from a node slack report. The IC test engine also generates cell-aware test patterns for each cell instance of each cell type in the IC design to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of a plurality of candidate defects characterized in the plurality of fault rules files. Each cell-aware test pattern is configured to sensitize and propagate a transition along the longest possible path to test small delay defects in cell instances of the fabricated IC chip.

Abstract: A method can be executed by at least one processor of a computer to generate synthetic Integrated Circuit (IC) layout patterns, where the method can optionally include accessing attribute values of the IC layout pattern features generated using IC layout patterns from at least one at least one previous generation semiconductor fabrication technology node.

Abstract: A method for adaptive error correction in quantum computing includes executing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In an embodiment, the method includes estimating, responsive to determining an initial state of the quantum processor, a runtime duration for a quantum circuit design corresponding to a quantum algorithm, the quantum processor configured to execute the quantum circuit design. In an embodiment, the method includes computing an error scenario for the quantum circuit design. In an embodiment, the method includes selecting, using the error scenario and the initial state of the quantum processor, a quantum error correction approach for the quantum circuit design. In an embodiment, the method includes transforming the quantum algorithm into the quantum circuit design, the quantum circuit design including a set of quantum logic gates.

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

Abstract: A method of simulating quantum gates includes shifting a Fock basis for the simulation such that the simulation can be performed in a smaller (e.g. truncated) Hilbert dimension space. To shift the Fock basis, non-orthonormalized basis states are first defined. The defined basis states are then orthonormalized to construct orthonormalized shifted Fock basis state. Matrix elements are determined for an operator in the orthonormalized shifted Fock basis and the operator is used to simulate the quantum gate in the shifted Fock basis.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design at a verification environment. Embodiments may also include performing a simulation of a portion of the electronic design in an X-propagation mode. Embodiments may further include determining whether the simulation is entering an element during a time range and determining whether a clock/reset associated with the element has an active X-edge. If the clock/reset has an active X-edge, embodiments may include preventing a recordation of coverage metrics during the time range.