Abstract: In a dissection method for layout patterns in a semiconductor device, a design layout is divided into a plurality of patches. A plurality of first dissection points for target layout patterns in the target patch and neighboring layout patterns in the neighboring patches are set based on vertexes of the target and neighboring layout patterns. At least one second dissection point for at least one exceptional layout pattern is set. The at least one exceptional layout pattern is a layout pattern in which the first dissection points are not set and which extends to pass through boundaries of one patch. A plurality of third dissection points for the target layout patterns and the neighboring layout patterns are set based on the first and second dissection points. The target layout patterns are divided into a plurality of target segments based on the first, second and third dissection points.

Abstract: Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.

Abstract: An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.

Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell uses unidirectional tracks for each of the multiple power vertical metal 3 layer tracks and power horizontal metal 2 tracks. One or more of the multiple vertical metal 3 layer posts are routed with a minimum length based on a pitch of power horizontal metal 2 layer straps. One or more vertical metal 1 posts used for a power connection or a ground connection are routed from a top to a bottom of an active region permitting multiple locations to be used for connections to one of the multiple power horizontal metal 2 layer straps. Two or more power horizontal metal 2 layer straps are placed within a power metal 2 layer track without being connected to one another.

Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes initializing a layout for fabricating an integrated circuit. A plurality of fill cells is inserted into the layout. The plurality of fill cells includes a plurality of fill line shapes that correspond to conductive lines of the integrated circuit. Thereafter, a design is inserted into the layout that includes a plurality of functional shapes. A conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality functional shapes are removed. The layout that includes the plurality of fill cells and the design is provided for fabricating the integrated circuit.

Abstract: The present disclosure relates to system(s) and method(s) for interactively controlling the course of a functional simulation of DUV/SUV. The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench generates a set of input data/packets as a stimulus to be processed by the DUV/SUV. The set of input data/packets is generated to simulate and verify the DUV/SUV. Further, the testbench identifies a pre-defined event at runtime during the simulation. Upon identification of the event, the testbench is configured to pause the simulation and transmit a notification message to a user indicating the occurrence of the event. Further, the testbench waits for a pre-defined time interval to receive one or more user inputs. The testbench further generates new stimulus based on the one or more user inputs and resumes the paused simulation with the new stimulus, thereby controlling the course of the functional simulation.

Abstract: The present disclosure discloses a charging control system, which includes: a master device, including a first USB interface and a first charging management circuit; at least one slave device, including a second USB interface and a second charging management circuit; a gating control circuit, which is arranged in the master device or the slave device, wherein an input terminal of the gating control circuit is coupled to the first USB interface and the second USB interface, and an output terminal of the gating control circuit is coupled to the first charging management circuit and the second charging management circuit to select and control a charging USB interface of the first charging management circuit and a charging USB interface of the second charging management circuit. Through the above mentioned way, multiple charging modes of the master device and the slave device may be implemented without software support.

Abstract: A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode.

Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

Abstract: A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit. The computing system also can perform a parasitic extraction process on the geometric layout design by utilizing the device-level layout design for the integrated circuit. The computing system implementing the parasitic extraction process can sub-divide a conductor in the device-level layout design into multiple sub-divided conductor portions based on conversion rules corresponding to the physical properties of layers for the integrated circuit described in a technology file. The computing system can generate a physical layout design of the integrated circuit from the device-level layout design having the sub-divided conductor portions based on the technology file.

Abstract: A system for implementing functional logics of a verification IP using a transaction level modeling (TLM) is provided. The system includes (A) a stimulus generator to initiate a transaction and transmit the transaction through a transaction level model interface, (B) a verification IP unit to receive and process the transaction and (C) a signal-level driver to toggle pins of the design under test (DUT) based on the processed transaction. The verification IP unit is configured to (a) divide functional logics of a verification IP unit into one or more finite state machines (FSMs) when a transaction is received from a stimulus generator, (b) define a set of state variables for each of the one or more FSMs, (c) implement a state class for each state of the one or more FSMs and (d) modify the functionality of the one or more FSMs.

Abstract: Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified to bring non-compliant periphery chip regions into compliance, in response to the determination that the portion of the first chip layout inside the tile area fails to comply with the one or more design rules. A multi-chip wafer is fabricated that includes the chip layouts.

Abstract: Methods and apparatus are provided for automatically extracting standard cells to form a standard cell library using raw multi-layer images of an IC. Accordingly, various embodiments involve: extracting the raw contact layer image from the raw multi-layer images; binarizing the raw contact layer image to generate a binarized contact layer image identifying a plurality of contact rows and a plurality of contact columns; determining a plurality of Vcc lines based on a subset of the plurality of contact rows having a periodic nature; extracting a plurality of binarized contact layer image strips from the binarized contact layer image; encoding each binarized contact layer image strip using feature vectors and column distance values; applying a model rule set to each encoded binarized contact layer image strip for detecting cell boundaries; extracting the standard cells based on the cell boundaries; and storing the extracted cells to form a standard cell candidate library.

Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include creating a plurality of library (lib) cells for a directional routing layer, and determining a lib cell of the plurality of lib cells for placement of at least one repeater for the directional routing layer. The operations may also include determining a route touch region corresponding to a pin region of the lib cell through which a route is going through and inserting the at least one repeater at the route touch region. The operations may also include swapping the at least one inserted repeater to at least one target lib cell of the plurality of lib cells.

Abstract: An approach is described for a method, system, and product, that includes identification/generation of a synthesized netlist for use in optimization and placement, generation and utilization of multiple uncertainty values for an early clock tree for guiding optimization and placed of circuit elements in a placeopt process that operates on a path by path basis. In some embodiments, the approach further comprises execution of clock tree synthesis, and routing the synthesized clock tree. In some embodiments, uncertainty values are propagated along data paths where each data path is associated with an uncertainty value, and where each path is optimized and placed on a path my path basis in order to meeting timing requirements and one or more design goals.

Abstract: A circuit arrangement includes a buffer, a height traversal circuit configured to generate a sequence of IFM height values in response to first control signals, a width traversal circuit configured to generate a sequence of IFM width values in response to second control signals, a control circuit, and an address generation circuit. The control circuit is configured to input an OFM height, an OFM width, a kernel height, and a kernel width; generate the first control signals at times based on the OFM height and the kernel height; and generate the second control signals at times based on the OFM width and the kernel width. The address generation circuit is configured to generate a sequence of addresses based on the sequences of IFM height values and IFM width values, provide the sequence of addresses to the buffer, and enable reading from the buffer.

Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.

Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.