Patents Examined by Arpan P Savla
  • Patent number: 11994994
    Abstract: A memory device includes a memory array and a memory controller operatively coupled to the memory array. The memory array includes memory cells to store memory data. The memory controller includes a prefetch buffer, a read address buffer including memory registers to store addresses of memory read requests received from at least one separate device, and logic circuitry. The logic circuitry is configured to store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer, and omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 28, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Aniket Akshay Saraf, Kaushik Kandukuri, Thirukumaran Natrayan, Saurbh Srivastava
  • Patent number: 11977481
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: May 7, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Patent number: 11972132
    Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: April 30, 2024
    Assignee: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, Tim Tuan, David Clarke
  • Patent number: 11971827
    Abstract: Methods, apparatus, systems and articles of manufacture to control address space isolation in a virtual machine are disclosed. An example apparatus includes an address width adjustor to identify a memory width value corresponding to a guest memory associated with a virtual machine (VM), and generate an expanded emulated memory width value. The example apparatus also includes a memory mirror manager to generate a first guest physical address (GPA) range based on the memory width value, and generate a second GPA range based on the expanded emulated memory width value. The example apparatus also includes an EPT generator to generate root paging structures of a first type of EPT with respective addresses within the first GPA range, and generate root paging structures of a second type of EPT with respective addresses within (a) the first GPA range and (b) the second GPA range.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Jun Tian, Kun Tian, Yu Zhang
  • Patent number: 11954045
    Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: David M. Durham, Michael LeMay, Santosh Ghosh, Sergej Deutsch
  • Patent number: 11947817
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for memory mapping to enhance data cube performance. In some implementations, a system accesses a data set that includes data to be processed into a data cube. The system generates a memory-mapped data cube that includes a plurality of files including different segments of the data cube. Generating the memory-mapped data cube includes allocating memory-mapped buffers in non-volatile data storage and responding to subsequent memory allocation requests with addresses for the buffers such that components of the data cube are accumulated in the buffers. The memory-mapped data cube is loaded by storing the files of the data cube in disk-based storage, mapping the stored files of the data cube to virtual memory addresses, and caching portions of the data cube in random-access memory.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: April 2, 2024
    Assignee: MicroStrategy Incorporated
    Inventors: Qianping Jiang, Cheng Guo, Rixin Liao, Cezary Raczko, Xiaoyan Yu
  • Patent number: 11934685
    Abstract: A quad-to-single (Q2S) data structure comprising a plurality of the Q2S mapping entries is maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes of the non-volatile memory device with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list. The linked list corresponds to a Q2S mapping entry associated with the QLC block stripe to be programmed.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael Winterfeld, Guanying Wu
  • Patent number: 11899949
    Abstract: Methods and systems are provided for configuring static memory in a device by analyzing a set of functionalities of a first device based on at least one use case wherein the at least one use case are associated with configuring available static memory in processing at least one functionality of the first device; configuring at least a first profile composed of the first part for memory allocation of the available static memory to a first processor, and a second part for memory allocation of the available static memory to a second processor of the first device; selecting the first profile either automatically or via a graphical user interface (GUI) by identifying a set of performance characteristics related to the functionality, and implementing the memory allocation by the first profile in processing the at least one functionality in the use case by the first device.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: February 13, 2024
    Assignee: DISH Network Technologies India Private Limited
    Inventors: Rakesh Eluvan Periyaeluvan, Gopikumar Ranganathan, Jayaprakash Narayanan Ramaraj
  • Patent number: 11893239
    Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit includes a first interface coupled to a host device and a second interface coupled to the HBM device. The logic circuit receives a first command from the host device through the first interface and converts the received first command to a first processing-in-memory (PIM) command that is sent to the HBM device through the second interface. The first PIM command has a deterministic latency for completion. The logic circuit further receives a second command from the host device through the first interface and converting the received second command to a second PIM command that is sent to the HBM device through the second interface. The second PIM command has a non-deterministic latency for completion.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 6, 2024
    Inventors: Krishna T. Malladi, Hongzhong Zheng
  • Patent number: 11893259
    Abstract: A storage system comprises a plurality of storage devices, and is configured to establish a production drive group comprising a first subset of the storage devices, using a first firmware-level configuration process, and to establish a stealth drive group comprising a second subset of the storage devices, using a second firmware-level configuration process, the storage devices of the stealth drive group thereby being separated at a firmware level of the storage system from the storage devices of the production drive group. The storage system is further configured to copy data of one or more logical storage volumes from the production drive group to the stealth drive group, and responsive to completion of the copying of the data of the one or more logical storage volumes from the production drive group to the stealth drive group, to initiate a firmware-level reconfiguration process for the storage devices of the stealth drive group.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: February 6, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Boris Giterman, Yaniv Sagron, Arieh Don
  • Patent number: 11868282
    Abstract: A network controller for coupling a host device to a data network, in accordance with network command blocks initiated in a request queue in the host device, includes a channel interface configured to couple to the data network, where the channel interface includes memory configured to store the network command blocks and processing circuitry configured to execute the network command blocks to move data between the host device and the data network, and a host interface configured to couple the network controller to the host device, and to move the network command blocks from the request queue in the host device to the memory using cache operations, including fetching one of the network command blocks from the request queue upon receipt from the host device of a message advising that a request queue location has changed.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 9, 2024
    Assignee: Marvell Asia Pte Ltd
    Inventors: Bradley Sonksen, Paul Nitza
  • Patent number: 11853586
    Abstract: Techniques are disclosed herein for improved copy data management functionality in storage systems. For example, a method receives copy usage data for one or more data copies associated with a storage array, wherein the copy usage data is indicative of a usage associated with each of the one or more data copies, and updates the one or more data copies with one or more usage tags based on the received copy usage data. Further, the method may then scan the one or more usage tags associated with each of the one or more data copies, select one or more storage tiers for at least a portion of the one or more data copies based on the scanning of the one or more usage tags, and cause at least a portion of the one or more data copies to be stored in the selected one or more storage tiers.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: December 26, 2023
    Assignee: EMC IP Holding Company LLC
    Inventor: Sunil Kumar
  • Patent number: 11841796
    Abstract: Methods, systems, and devices for scratchpad memory in a cache are described. A device may operate a portion of a volatile memory in a cache mode having non-deterministic latency for satisfying requests from a host device. The device may monitor a register with an output pin that is associated with the portion and indicative of an operating mode of the portion. Based on or in response to monitoring the output pin, the device may determine whether to change the operating mode of the portion from the cache mode to a scratchpad mode having deterministic latency for satisfying requests from the host device.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: December 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chinnakrishnan Ballapuram, Saira Samar Malik, Taeksang Song
  • Patent number: 11829630
    Abstract: Described is a system (and method) for providing multiple types of granular delete operations for a cloud-based object storage. The system may include a server that acts as an intermediary between a client device and an object storage that stores client data. The server may allow a client to perform a hard delete (or permanent) delete and a soft delete. The server may perform a specialized processing to synthetically create the soft delete feature using a permanent object delete operation provided by the object storage. The specialized processing may include manipulating retention periods associated with objects depending on whether the object is subject to a hard delete or a soft delete. As a result, the server may provide the ability for clients to perform a soft delete at an object level using existing storage level APIs that do not directly support such a feature.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: November 28, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Ravi Vijayakumar Chitloor, Sunil Yadav, Shelesh Chopra, Amarendra Behera, PrabhatKumar Dubey, Deependra Singh, Jigar Bhanushali, Himanshu Arora, Tushar Dethe
  • Patent number: 11822801
    Abstract: Configuring systems to provide host access may include: configuring a stretched volume; and performing processing that allows the host access to the stretched volume. The processing may include: receiving a first command to create a first host object for access control for the host in the first data storage system; in response to receiving the first command, performing first processing including: creating the first host object that includes an initiator set of the host; and creating a second host object on the second data storage system, wherein the second host object includes the initiator set and specifies access control in the second data storage system for the host; receiving a second command to map the stretched volume to the first host object; and in response to receiving the second command, granting the host access to the stretched volume on the first data storage system and the second data storage system.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: November 21, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Dmitry Tylik, Dave J. Lindner, Girish Sheelvant, Nagasimha G. Haravu
  • Patent number: 11822792
    Abstract: Transforming data that is provided by a first instance of an application that uses application-instance specific data includes determining if a component of the data is an application-instance specific component and, if the component is an application-instance specific component, transforming the component either at a storage system containing the data or as the component is being accessed by a second instance of the application, different from the first instance. Transforming the component at a storage system containing the data may be performed independently of any accesses of the data. Transforming the component at a storage system containing the data may be performed by the storage system. The first instance of the application may run on a first host and the second instance of the application may run on a second host different from the first host. The first and second instances of the application may run on a same host.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 21, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Brett A. Quinn, Douglas E. LeCrone
  • Patent number: 11816342
    Abstract: A method includes sending, from an application layer, a chunk size setting to an erasure coding layer. The method further includes receiving, at the application layer, user data. The method further includes aligning, at the application layer, the user data based on the chunk size setting. The method further includes sending the aligned user data to the erasure coding layer. The method further includes partitioning, at the erasure coding layer, the aligned user data into a first data chunk and a second data chunk. The method further includes generating, at the erasure coding layer, a parity chunk based on the first data chunk and the second data chunk. The method further includes sending, from the erasure coding layer, the first data chunk, the second data chunk, and the parity chunk to a storage system.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rekha Pitchumani, Yang Seok Ki
  • Patent number: 11809334
    Abstract: An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: November 7, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Neil Whyte, Michael Chandler-Page, Pradeep Saminathan, Jon Eklund
  • Patent number: 11775421
    Abstract: An information processing system, computer readable storage medium, and a method for managing computer memory. The method includes deploying at least one memory allocator on a computing system which includes a multi-user computing system or a cloud computing system; dynamically allocating, by the at least one memory allocator, an amount of dynamically allocated memory for use by an executing program at runtime; and determining a cost to charge a user based on the amount of memory that has been allocated. Multiple billing methods can be used including: restricting the amount of dynamically allocated memory available to the user based on how much the user is paying; charging the user a fee which grows with an amount of dynamically allocated memory consumed; charging the user higher fees during higher periods of dynamically allocated memory usage; and charging the user a low fee for maintaining dynamically allocated memory usage below a threshold.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventor: Arun Kwangil Iyengar
  • Patent number: 11763906
    Abstract: Methods, systems, and devices for degradation signaling for a memory device are described. In one example, a method in accordance with the described techniques may include monitoring, at a memory device, an operational characteristic of the memory device. For example, the threshold voltage of one or more transistors within the memory device may be monitored. The memory device may identify a degradation of the memory device based at least in part on the monitored operational characteristic. Based on identifying the degradation, the memory device may signal, to a host device, an indication of the degradation of the memory device.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Todd A. Merritt