Abstract: Data traffic comprising data packets communicated between a memory sub-system and a host system is monitored by a processing device at the memory sub-system. Data packets are classified according to packet type. Log data comprising a frequency and latency information associated with each packet type is generated. The log data is stored in a memory component of the memory sub-system.

Abstract: Scalable segment cleaning for log-structured file systems (LFSs) includes determining counts of segment cleaners and virtual nodes, with each virtual node being associated with a plurality of objects. Each virtual node is assigned to a selected segment cleaner. Based at least on the assignments, performing, for each virtual node, segment cleaning of the objects by the assigned segment cleaner. A portion, less than all, of the virtual nodes are reassigned to a newly selected segment cleaner based on a change of the count of the segment cleaners and/or a change of the count of the virtual nodes. Based at least on the reassignments, segment cleaning of the objects is performed, for each reassigned virtual node, by the reassigned segment cleaner. In some examples, the objects comprise virtual machine disks (VMDKs) and the segment cleaning uses a segment usage table (SUT) to track segment usage and identify segment cleaning candidates.

Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

Abstract: Utilizing a storage replica data structure includes receiving, at a hyper-kernel running on a computing node in a plurality of interconnected computing nodes, an indication of an operation pertaining to at least one of a guest physical memory address or a stable storage address. A guest operating system is run on a virtual environment that is defined by a set of hyper-kernels running on the plurality of interconnected computing nodes. It further includes updating a storage replica data structure. The storage replica data structure comprises a set of entries. The set of entries in the storage replica data structure comprises associations among guest physical memory addresses, physical memory addresses, and stable storage addresses.

Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.

Abstract: Various embodiments for optimizing memory bandwidth in a disaggregated computing system, by a processor device, are provided. Respective memory devices are assigned to respective processor devices in the disaggregated computing system, the disaggregated computing system having at least a pool of the memory devices and a pool of the processor devices. An analytic function is performed on data resident in the pool of the memory devices using memory bandwidth not currently committed to a primary compute task.

Abstract: A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.

Abstract: A computing device and an operating method thereof are provided. The computing device includes a memory and a processor configured to: perform a first compression on a data object stored in the memory according to a first compression method, store the first compressed data object in a swap data storage area, and reclaim a portion of the memory in which the first compressed data object was stored; register information about the first compressed data object in a first management table; obtain the information about the first compressed data object from the first management table based on a usage ratio of the processor; and perform a second compression on the first compressed data object according to a second compression method, store the second compressed data object in the swap data storage area, and reclaim a portion of the swap data storage area in which the first compressed data object was stored.

Abstract: A storage system includes: a storage drive having a storage medium storing a data; and a plurality of storage control units having a processor, a memory, and a port to process the data input and output to and from the storage drive, in which information related to a list of the storage control units mounted on the storage system and a maximum number of the storage control units that can be mounted on the storage system is allowed to be stored, and in which, when the storage control unit is replaced, it is determined whether the configuration to be migrated from the storage control unit to be reduced to the storage control unit to be added is migrated directly or via another storage control unit based on the number of the mounted storage control units and the maximum number of the storage control units that can be mounted.

Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.

Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

Abstract: A processor employs a set of bits to indicate values of portions of registers of a register file. In response to a specified instruction indicating an expected change of instruction types to be executed, the processor sets one or more of the bits and, for subsequent instructions, interprets corresponding portions of the registers as having a specified value (e.g., zero). By employing the set of bits to set the values of the register portions, rather than setting the individual portions of the registers to the specified value, the processor conserves processor resources (e.g., power) when the processor transitions between executing instructions of different types.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for tracking memory usage data on a memory controller system and providing a mechanism whereby one or multiple accessing agents (e.g., computing nodes, applications, virtual machines) can access memory usage data for a memory resource managed by a memory controller. Indeed, the systems described herein facilitate generation of and access to heatmaps having memory usage data thereon. The systems described herein describe features and functionality related to generating and maintaining the heatmaps as well as providing access to the heatmaps to a variety of accessing agents. This memory tracking and accessing is performed using low processing overhead while providing useful information to accessing agents in connection with memory resources managed by a memory controller.

Abstract: A method for accessing data where the method includes receiving, by an access client executing in user space, a request to read data that includes a file system identifier and an offset, identifying a storage server associated with the data, generating a command to copy the data to memory, and sending the command to the storage server.

Abstract: The present disclosure relates to a unified memory apparatus having a unified storage medium and one or more processing units. The unified memory apparatus can include a first storage module having a first plurality of storage cells, and a second storage module having a second plurality of storage cells, each of the first and second plurality of storage cells configured to store data and to be identified by a unique cell identifier. The one or more processing units are in communication with the unified storage medium and the processing units are configured to receive a first input data from one of the first plurality of storage cells, receive a second input data from one of the second plurality of storage cells, and generate an output data based on the first and second input data.

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks, wherein the plurality of memory blocks includes one or more first memory blocks, each storing at least invalid data and one or more second memory blocks, each of which is blank. The controller is configured to determine a time or a period for performing garbage collection to secure an additional second memory block based at least on a transition speed representing a speed in which the second memory blocks is converted to the first memory blocks, the transition speed being determined based on a change between a first count of the first memory blocks and a second count of the second memory blocks.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Memory controller systems, methods and apparatus for memory access and scheduling are herein disclosed. In some aspects, a memory controller includes a clock, a first interface to be coupled with a first memory device via a common memory channel, and a second interface to be coupled with a second memory device via the common memory channel. The memory controller also includes a register to store data to store data to indicate an access scheme to process access requests to the first memory device according to a first timing scheme and issue access requests to the second memory device according to a second timing scheme. The memory controller further includes logic to cause the access scheme to be implemented in order to issue access requests to the first memory device or to issue access requests to the second memory device via the common memory channel.

Abstract: A data storage system includes a memory including a plurality of memory cells; and control logic configured to receive a first data string and determine a data type of the first data string. If the first data string is a combination command, the control logic obtains a plurality of sub-commands based on the first data string. Meanwhile, the control logic receives a second data string, determines that it represents an address, and decodes the address. While decoding the address or otherwise processing the second data string, the control logic performs a system operation specified by one of the sub-commands. The control logic also performs a memory operation, specified by another of the sub-commands, on one or more of the plurality of memory cells in accordance with the decoded address.