Patents Examined by Asok Kumar Sarkar
  • Patent number: 10079260
    Abstract: A solid-state image sensor including a substrate having a photoelectric conversion element disposed therein, the photoelectric conversion element converting an amount of incident light into a charge amount, a memory unit disposed at a side of the photoelectric conversion element, the memory unit receiving the charge amount from the photoelectric conversion element, a first light-shielding section formed at a first side of the memory unit and disposed between the charge accumulation region and the photoelectric conversion element, and a second light-shielding section formed at a second side of the memory unit such that the second side is opposite the first side.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 18, 2018
    Assignee: Sony Corporation
    Inventor: Takeshi Takeda
  • Patent number: 9923063
    Abstract: A group III nitride composite substrate with a diameter of 75 mm or more includes a support substrate and a group III nitride film with a thickness of 50 nm or more and less than 10 ?m that are bonded to each other. A ratio st/mt of a standard deviation st of the thickness of the group III nitride film to a mean value mt of the thickness thereof is 0.01 or more and 0.5 or less, and a ratio so/mo of a standard deviation so of an absolute value of an off angle between a main surface of the group III nitride film and a plane of a predetermined plane orientation to a mean value mo of the absolute value of the off angle is 0.005 or more and 0.6 or less.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: March 20, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Ishibashi, Takuya Yanagisawa, Koji Uematsu, Yuki Seki, Yoshiyuki Yamamoto
  • Patent number: 9917125
    Abstract: A back-side imager includes a matrix of photosites in an active layer. An interconnect layer covers the active layer. A layer of germanium is positioned between the active layer and the interconnect layer.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: March 13, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 9349642
    Abstract: A method of forming a contact layer on a substrate having a contact hole to make a contact between the substrate and a buried metal material, includes disposing the substrate in a chamber, introducing a Ti source gas, a reducing gas and an Si source gas into the chamber, and converting the Ti source gas, the reducing gas and the Si source gas into plasma to form a TiSix film on the substrate. A portion of the TiSix film in a bottom of the contact hole corresponds to the contact layer.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: May 24, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Seishi Murakami, Takaya Shimizu, Satoshi Wakabayashi
  • Patent number: 8361819
    Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yu-Sik Kim
  • Patent number: 8349652
    Abstract: There is provided a three-dimensional integrated circuit manufacturing method for temporarily attaching a chip to a transcription substrate, and securely detaching the chip from the transcription substrate when the chip is transferred to a supporting substrate. When a chip is temporarily attached to a transcription substrate, by evaporating a liquid existing between the chip and the transcription substrate, the solids of the chip and the transcription substrate can be attached to each other. Accordingly, the chip can be temporarily attached to the transcription substrate so as not to be deviated from its own position. Further, by setting adhesive strength between the chip and a supporting substrate to be higher than that between the chip and the transcription substrate, the chip can be securely detached from the transcription substrate when the chip is transferred from the transcription substrate to the supporting substrate.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: January 8, 2013
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Mitsumasa Koyanagi, Takafumi Fukushima, Masahiko Sugiyama
  • Patent number: 8343867
    Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Yu-Ying Hsu, Chi-Ju Lee, Sin-Hua Wu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Patent number: 8263428
    Abstract: This disclosure provides polymer electrolytes for dye-sensitized solar cells that can not only prevent electrolytes from leaking, but also exhibit a higher solar conversion efficiency when compared with conventional polymer electrolytes, whereby the polymer electrolytes are applicable to a process for manufacturing dye-sensitized solar cells with a large surface area or flexible dye-sensitized solar cells, and methods for manufacturing modules of dye-sensitized solar cells using the same.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 11, 2012
    Assignee: Toray Advanced Materials Korea Inc.
    Inventors: Chang-Hoon Sim, Sang-Pil Kim, Ki-Jeong Moon
  • Patent number: 7393729
    Abstract: [Problem] To provide technology that allows, by controlling a crystal orientation, forming a crystalline semiconductor film aligned in orientation and obtaining a crystalline semiconductor film whose impurity concentration is reduced. [Means, for Resolution] On an insulating surface, a first semiconductor region made of an amorphous semiconductor is formed, a continuous wave laser beam is scanned from one end of the first semiconductor region to the other end thereof, thereby the first semiconductor region is once melted and crystallized, thereafter in order to form an active layer of a TFT the first semiconductor region is etched, and thereby a second semiconductor region is formed. In a pattern of the second semiconductor region formed by the etching, in order to improve a field-effect mobility in the TFT, a scanning direction of the laser beam is allowed roughly coinciding with a channel length direction in a thin film transistor. [Selected Drawing] FIG. 1.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: July 1, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7393707
    Abstract: An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, and diffusion of alkali metals from the EL element 203 formed by ink jet method into TFTs is prevented. Further, the third passivation film 45 prevents penetration of moisture and oxygen from the TFTs, and suppress degradation of the EL element 203 by dispersing the heat generated by the EL element 203.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: July 1, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kunitaka Yamamoto, Toshimitsu Konuma
  • Patent number: 7387939
    Abstract: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventor: H. Montgomery Manning
  • Patent number: 7384867
    Abstract: Methods for the deposition of tungsten films are provided. The methods include depositing a nucleation layer by alternatively adsorbing a tungsten precursor and a reducing gas on a substrate, and depositing a bulk layer of tungsten over the nucleation layer.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: June 10, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Ken K. Lai, Jeong Soo Byun, Frederick C. Wu, Ramanujapuran A. Srinivas, Avgerinos Gelatos, Mei Chang, Moris Kori, Ashok K. Sinha, Hua Chung, Hongbin Fang, Alfred W. Mak, Michael X. Yang, Ming Xi
  • Patent number: 7375383
    Abstract: A gallium nitride-based III-V Group compound semi-conductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: May 20, 2008
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 7374963
    Abstract: The present invention advantageously provides for, in different embodiments, low-cost deposition techniques to form high-quality, dense, well-adhering Group IBIIIAVIA compound thin films with macro-scale as well as micro-scale compositional uniformities. In one embodiment, there is provided a method of growing a Group IBIIIAVIA semiconductor layer on a base, and includes the steps of depositing on the base a film of Group IB material and at least one layer of Group IIIA material, intermixing the film of Group IB material and the at least one layer of Group IIIA material to form an intermixed layer, and forming over the intermixed layer a metallic film comprising at least one of a Group IIIA material sub-layer and a Group IB material sub-layer. Other embodiments are also described.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: May 20, 2008
    Assignee: Solopower, Inc.
    Inventor: Bulent M. Basol
  • Patent number: 7375025
    Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: May 20, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
  • Patent number: 7375014
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7371666
    Abstract: A process for producing brightly photoluminescent silicon nanoparticles with an emission spanning the visible spectrum is disclosed. In one aspect, the process involves reacting a silicon precursor in the presence of a sheath gas with heat from a radiation beam under conditions effective to produce silicon nanoparticles and acid etching the silicon nanoparticles under conditions effective to produce photoluminescent silicon nanoparticles. Methods for stabilizing photoluminescence of photoluminescent silicon nanoparticles are also disclosed.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: May 13, 2008
    Assignee: The Research Foundation of State University of New York
    Inventors: Mark T. Swihart, Xuegeng Li, Yuanqing He
  • Patent number: 7368383
    Abstract: A method for treating a copper surface of a semiconductor device provides exposing the copper surface to a citric acid solution after the surface is formed using CMP (chemical mechanical polishing) or other methods. The citric acid treatment may take place during a cleaning operation that takes place in a wafer scrubber, or subsequent to such an operation. The citric acid treatment removes copper oxides that form on copper surfaces exposed to the environment and prevents hillock formation during subsequent high temperature operations. The copper surface is then annealed and the annealing followed by an NH3 plasma treatment which again removes any copper oxides that may be present. The NH3 plasma operation roughens exposed surfaces improving the adhesion of subsequently-formed films such as a dielectric film preferably formed in-situ with the NH3 plasma treatment. The subsequently-formed film is formed over an oxide-free, hillock-free copper surface.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: May 6, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chi Lin, Francis Wang, Wen-Long Lee, Sez-An Wu
  • Patent number: 7368317
    Abstract: The invention relates to a method of producing an n-type diamond. The inventive method comprises an n-doping stage during which a donor species is vacuum diffused in a diamond that was initially doped with an acceptor, in order to form donor groups containing the donor species, at a temperature that is less than or equal to the dissociation temperature of the complexes formed between the acceptor and the donor species.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: May 6, 2008
    Assignees: Centre National de la Recherche Scientifique-CNRS, Universite de Versailles St-Quentin En Yvelines
    Inventors: Jacques Paul Marie Chevallier, Zephirin Symplice Teukam, Dominique Ballutaud
  • Patent number: 7358194
    Abstract: A method is provided for forming a Si film in sequential deposition process. The method includes providing a substrate in a process chamber, forming a chlorinated Si film by exposing the substrate to a chlorinated silane gas, and dry etching the chlorinated Si film to reduce the chlorine content of the Si film. The Si film may be deposited selectively or non-selectively on the substrate and the deposition may be self-limiting or non-self-limiting. Other embodiments provide a method for forming SiGe films in a sequential deposition process.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: April 15, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Anthony Dip, Allen John Leith, Seungho Oh