Abstract: This invention provides methods of fabricating semiconductor devices, wherein an alloy layer is formed on a semiconductor substrate to form a substrate structure, which methods include using an aqueous solution diluted ammonia and peroxide mixture (APM) to perform cleaning and/or wet etching treatment steps on the substrate structure.

Abstract: A method of manufacturing an element having a microstructure of an excellent grating groove pattern or the like is obtained. This method of manufacturing an element having a microstructure comprises steps of forming a metal layer on a substrate, forming a dot column of concave portions on the surface of the metal layer and anodically oxidizing the surface of the metal layer formed with the dot column of concave portions while opposing this surface to a cathode surface thereby forming a metal oxide film having a grating groove pattern. When the interval between the concave portions of the dot column is reduced, therefore, a linear grating groove pattern having a large depth with a uniform groove width along the depth direction is easily formed in a self-organized manner.

Abstract: A manufacturing method of a semiconductor device comprises: (a) setting up a paste including a resin on an electrical connection part which is electrically connected to a semiconductor substrate; (b) setting up a soldering material above the electrical connection part so as to be in contact with the paste; and (c) forming an external terminal from the soldering material and forming a reinforcement from the paste by fusing the soldering material and the paste. The reinforcement exposes part of the external terminal and covers a periphery of an edge of a base connected to the electrical connection part of the external terminal.

Abstract: A process and system are provided for processing at least one section of each of a plurality of semiconductor film samples. In these process and system, the irradiation beam source is controlled to emit successive irradiation beam pulses at a predetermined predetermined repetition rate. Using such emitted beam pulses, at least one section of one of the semiconductor film samples is irradiated using a first sequential lateral solidification (“SLS”) technique and/or a first uniform small grained material (“UGS”) techniques to process the such sections) of the first sample. Upon the completion of the processing of this section of the first sample, the beam pulses are redirected to impinge at least one section of a second sample of the semiconductor film samples. Then, using the redirected beam pulses, such sections) of the second sample are irradiated using a second SLS technique and/or a second UGS technique to process the at least one section of the second sample.

Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.

Abstract: The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter and a film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter and that is strained by the matching layer. This process includes transfer of the film to a receiving substrate. The invention also relates to the semiconductor structures that can be produced by the process.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.

Abstract: A method for smoothing areas of a structure made of a first material having a predetermined first glass transition temperature on a carrier includes the steps of: (1) applying a second material having a predetermined second glass transition temperature, so that the surface of the structure of the first material is at least partially covered by the second material; (2) increasing the temperature of the first material to a first predeterminable temperature, which is greater than the first glass transition temperature; and (3) lowering the temperature of the first material below the first glass transition temperature of the first material.

Abstract: According to the invention, the thin film having the thickness controlled desirably can be easily formed using common semiconductor processes. Provided is a coating liquid for forming the porous film having an excellent dielectric property and mechanical property. Specifically, the coating liquid for forming a porous film comprises the condensation product obtained by condensation of one or more silicate compounds represented by the formula (X2O) i(SiO2)j(H2O)k and one more organosilate compounds represented by the formula (X2O)a(RSiO1.5)b(H2O)c. Thus, the porous insulating film having sufficient mechanical strength and dielectric properties for use in the semiconductor manufacturing process can be manufactured.

Abstract: A method of fabricating a semiconductor device, includes (a) forming an oxide film entirely over a silicon substrate on which a MOS transistor is fabricated, (b) carrying out first thermal-annealing to the silicon substrate, (c) removing the oxide film in an area where later mentioned silicide is to be formed, (d) forming a metal film entirely over the silicide substrate, (e) carrying out second thermal-annealing to the silicon substrate to form silicide in the area, and (f) removing the metal film having been not reacted with the silicon substrate.

Abstract: A method of manufacturing a crystalline wafer that includes implanting first atomic species in a donor substrate to form a region of weakness at a first depth therein and configured to facilitate detachment of a first layer of the donor substrate from a remaining portion of the donor substrate. The first layer and remaining portion are disposed on opposite sides of the region of weakness. The method also includes implanting second atomic species in the donor substrate to form a gettering region at a second depth therein that is different than the first depth to reduce or minimize migration of the implanted first atomic species past the gettering region. This reduces or minimizes an increase in roughness of a surface produced on the first layer after detachment thereof from the remaining portion at the region of weakness.

Abstract: A method of making an integrated circuit chip is provided, which combines a smart grading implant with a diffusion retarding implant, e.g., to improve short channel effect controllability and improve dopant grading in the source/drain regions. Using a smart grading implant, a relatively low-energy high-dose implant is performed before a relatively low-energy high-dose implant. Hence, a relatively high-energy low-dose implant of ions is performed into a source/drain region of a substrate. A diffusion retarding implant is performed into the source/drain region of the substrate. Then after performing the high-energy low-dose implant and the diffusion retarding implant (together, overlapping, or separately), a relatively low-energy high-dose implant of ions is performed into the source/drain region of the substrate.

Abstract: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by metal wires; and chip capacitors mounted on the semiconductor chip to reduce power source noise.

Abstract: A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.

Abstract: Metal organic chemical vapor deposition (MOCVD) may be utilized in methods of forming an (111) oriented PZT ferroelectric layer at a lower temperature, a ferroelectric capacitor and methods of fabricating, and a ferroelectric memory device using the same may be provided. Using the metal organic chemical vapor deposition, ferroelectric layers, capacitors, and memory devices, which may be fabricated and may have (111) preferred oriented crystal growth.

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract: According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

Abstract: A method for producing thin layers of a semiconductor material from a donor wafer, which comprises in succession forming a first weakened region in a donor wafer below a first face and at a depth corresponding substantially to the thickness of a first thin layer to be transferred, detaching the first thin layer having upper and lower boundaries defined by the first face and the first weakened region, forming a second weakened region in the donor wafer after detachment of the first thin layer and without conducting an intermediate recycling step, with the second weakened region formed below a second face of the donor wafer and at a depth corresponding substantially to the thickness of a second thin layer to be transferred, and detaching the second thin layer having upper and lower boundaries defined by the second face and the second weakened region. Resultant semiconductor-on-insulator structures are also included.

Abstract: Method of making an integrated passive, such as a high quality decoupling capacitor, includes providing a first temporary support, a silicon capacitor wafer, and providing an oxide layer and a conductive layer on it. Then, a second temporary support, such as a handle wafer, may be attached to the capacitor wafer (i.e., to the oxide layer on it) by an adhesive bond. The capacitor wafer may then be destructively removed. A second conductive layer is then provided on an exposed backside of the oxide layer. The addition of a second electrode on the second conductive layer yields the desired high quality capacitor. Further processing steps, such as solder bumping, may be carried out while the capacitor wafer is still attached to the handle wafer. When the desired processing steps are complete, the handle wafer is removed, and the relatively thin high quality integrated capacitor wafer results.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.