Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad. In particular, a conductive structure may be formed on the insulating layer and on the exposed portion of the conductive pad. The conductive structure may include a base layer of titanium-tungsten (TiW) and a conduction layer of at least one of aluminum and/or copper. Moreover, the base layer of the conductive structure may be between the conduction layer and the insulating layer. Related devices are also discussed.

Abstract: This invention presents a novel method to form uniform or heterogeneous, straight or curved and size-controllable nanostructures including, for example, nanotubes, nanowires, nanoribbons, and nanotapes, including SiNW, using a nanochannel template. In the case of semiconductor nanowires, doping can be included during growth. Electrode contacts are present as needed and may be built in to the template structure. Thus completed devices such as diodes, transistors, solar cells, sensors, and transducers are fabricated, contacted, and arrayed as nanowire or nanotape fabrication is completed. Optionally, the template is not removed and may become part of the structure. Nanodevices such as nanotweezers, nanocantilevers, and nanobridges are formed utilizing the processes of the invention.

Abstract: According to one embodiment of the invention, a method for integrating low Schottky barrier metal source/drain includes providing a substrate, forming an epitaxial SiGe layer outwardly from the substrate, forming an epitaxial Si layer outwardly from the SiGe layer, and forming a metal source and a metal drain.

Abstract: The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasing current drive in some embodiments.

Abstract: A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold.

Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.

Abstract: A manufacturing method for a semiconductor device, including the steps of: forming a passivation film that covers a surface of a semiconductor substrate on which electrodes have been formed, in which an opening is formed so as to expose a predetermined electrode from among the electrodes; forming a diffusion prevention plug of a first metal in the vicinity of the opening in the passivation film; supplying a second metal material to the surface of the semiconductor substrate on which the diffusion prevention plug has been formed, so as to form a seed layer of the second metal; forming a resist film that covers the seed layer and in which an opening is formed so as to expose a predetermined region of the seed layer on the diffusion prevention plug; supplying a third metal material into the opening in the resist film so as to form a protrusion electrode of the third metal; removing the resist film after the step of forming a protrusion electrode; and removing the seed layer after the step of forming a protrusion

Abstract: A low stress, protective coating for a semiconductor device and a method for its manufacture. A preferred embodiment comprises coating the top surface of a semiconductor die with polyimide except for corner regions of the die. Not having corners in the polyimide protective overcoat generally reduces shear stresses in the die. Reducing stress, in turn, generally reduces the occurrence of problems such as fracture, delamination, or cracking within the die. A low stress coating may be particularly advantageous in semiconductor devices having low-k insulating materials, which are generally of low mechanical strength.

Abstract: The present invention provides a semiconductor wafer comprising an insulated board of sapphire or the like having translucency, which is provided with a positioning orientation flat at a peripheral portion thereof, and a silicon thin film formed over the entire one surface of the insulated board. In the semiconductor wafer, ions are implanted in an area containing the orientation flat at a peripheral portion of the silicon thin film to amorphize silicon. Thus, the translucency at the amorphized spot is eliminated and accurate positioning using the conventional optical sensor can be performed.

Abstract: A method of manufacturing a MIM capacitor and a interconnecting structure using a damascene process. The MIM capacitor and the first interconnecting structure can be formed at equal depths.

Abstract: A method for manufacturing a semiconductor structure comprising clusters and/or nanocrystals of silicon described which are present in distributed form in a matrix of silicon compound. The method comprises the steps of depositing a layer of thermally nonstable silicon compound having a layer thickness in the range between 0.5 nm and 20 nm especially between 1 nm and 10 nm and in particular between 1 nm and 7 nm on a support and thermal treatment at a temperature sufficient to carry out a phase separation to obtain clusters or nanocrystals of silicon in a matrix of thermally stable silicon compound. The claims also cover semiconductor structures having such distributed clusters or nanocrystals of silicon The method described enables the economic production of high density arrays of silicon clusters or nanocrystals with a narrow size distribution.

Abstract: There is disclosed a method of processing a substrate, which comprises applying a surfactant or a water soluble polymer agent onto a surface of a substrate to be processed, and sliding a circumferential portion of the substrate and a polishing member against each other to polish the circumferential portion of the substrate.

Abstract: The invention relates to a method for manufacturing a material compound wafer by forming a predetermined splitting area in a source substrate; attaching the source substrate to a handle substrate to form an assembly; heating the assembly for weakening the predetermined splitting area; and determining a degree of weakening of the predetermined splitting area which evidences the physical strength of the predetermined splitting area during or after heating to detect anomalies that may lead to damage of the source substrate, handle or assembly. The degree of weakening is advantageously determined in-situ and may be determined continuously or periodically during the heating. The invention further relates to an apparatus for thermal annealing device used in the manufacturing process of a material compound wafer.

Abstract: Embodiments of the present invention are directed to methods for fabricating microscale-to-nanoscale interfaces. In numerous embodiments of the present invention, hybrid microscale/nanoscale crossbar multiplexers/demultiplexers provide for selection and control of individual nanowires through a set of microscale signal lines. In order to overcome the difficulty of aligning nanowires with submicroscale and microscale signal lines, at least a portion of the interconnections between nanowires and sub-microscale or microscale signal lines are randomly generated by one of various connection-fabrication methods. Addresses for individual nanowires, or groups of nanowires, can be discovered by testing the microscale-to-nanoscale interfaces.

Abstract: A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substrate in a region not covered with the barrier layer by introducing pure dry oxygen, and performing a wet oxidation process to form a second field oxide adjacent the first field oxide by introducing hydrogen and oxygen. The method of the present invention can improve the quality and electrical property of the semiconductor device, increase the yield, and reduce the cost.

Abstract: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.

Abstract: A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. Another method includes forming a high density plasma proximate a substrate; flowing gases into the plasma, at least some of the gases forming silicon dioxide; depositing the silicon dioxide formed from the gases over the substrate; and while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. As an alternative, the method may include not cooling the substrate with a coolant gas while depositing the silicon dioxide.

Abstract: Methods of filling gaps on semiconductor substrates with dielectric film are described. The methods reduce or eliminate sidewall deposition and top-hat formation. The methods also reduce or eliminate the need for etch steps during dielectric film deposition. The methods include treating a semiconductor substrate with a hydrogen plasma before depositing dielectric film on the substrate. In some embodiments, the hydrogen treatment is used is conjunction with a high rate deposition process.

Abstract: A thermal treatment apparatus 1 includes a reaction tube 2 for containing wafers 10 contaminated with organic substances having a heater 12 capable of heating the reaction tube; a first gas supply pipe 13 for carrying oxygen gas into the reaction tube 2; and a second gas supply pipe 14 for carrying hydrogen gas into the reaction tube 2. Oxygen gas and hydrogen gas are supplied through the first gas supply pipe 13 and the second gas supply pipe 14, respectively, into the reaction tube 2, and the heater 12 heats the reaction tube 2 at a temperature capable of activating oxygen gas and hydrogen gas. A combustion reaction occurs in the reaction tube 2 and thereby the organic substances adhering to the wafers 10 are oxidized, decomposed and removed.