Abstract: The present invention relates to a method for forming LED. In the present invention, LED dies are defined by photolithography and etching processes to replace a cutting step, and a metal substrate of the LED is formed by chemical or physical method.

Abstract: In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.

Abstract: A thin film made of an amorphous material having a supercooled liquid phase region is formed on a substrate. Then, the thin film is heated to a temperature within the supercooled liquid phase region and is deformed by its weight, mechanical external force, electrostatic external force or the like, thereby to form a thin film-structure. Thereafter, the thin film-structure is cooled down to room temperature, which results in the prevention of the thin film's deformation.

Abstract: A method of forming a ferroelectric film including a complex oxide of PZT family on a metal film formed of Pt by using a metalorganic chemical vapor deposition method. At first, supply of Pb is started to form an alloy film of Pb and Pt on the metal film. Supply of Ti is then started to form an initial crystal nuclei of PbTiO3 on the alloy film. Then, supply of Zr is started to form a crystal grown layer of the complex oxide of PZT family on the initial crystal nuclei.

Abstract: A method for improving the properties of tunable etch resistant anti-reflective coatings (TERA) is disclosed. The method includes annealing the deposited layer of TERA in an environment containing at least one of hydrogen and deuterium. The annealed layer has an increased concentration of hydrogen and/or deuterium as compared to the deposited film, and may also have an additional concentration of hydrogen or deuterium at the interface between the substrate and the layer of TERA.

Abstract: Measure of forming an EL layer by selectively depositing through evaporation a material for forming the EL layer at a desired location is provided. When a material for forming an EL layer is deposited, a mask (113) is provided between a sample boat (111) and a substrate (110). By applying voltage to the mask (113), the direction of progress of the material for forming the EL layer is controlled to be selectively deposited at a desired location.

Abstract: A trench device with collar oxide for isolation. A buried trench capacitor is formed in a lower portion of a deep trench in a substrate. A conductive layer, surrounded by a collar insulating layer and lower than the collar insulating layer, is deposited in an upper portion of the trench. The collar insulating layer lining the trench is partially removed to expose a portion of the surface of the substrate such that a portion of the conductive layer contacts the substrate. A buried strap is formed where the substrate contacts the conductive layer, as a single-side buried strap. The other portions of the conductive layer are isolated from the substrate by the collar insulating layer. Thus, conventional shallow trench isolation (STI) structure is omitted.

Abstract: In one aspect, the invention includes a method of forming a silicon dioxide layer, comprising: a) forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, comprising: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C.

Abstract: The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasing current drive in some embodiments.

Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

Abstract: Methods and systems are provided for patterning a non conductive dielectric on a surface of a conductive polymer. The conductive polymer can be part of an organic memory cell. Hydrogen ions created form molecular hydrogen being exposed to short wave length radiation, are employed as mobile positive ion charge carriers to create a non-conductive die-electric pattern on a conductive and/or semiconductive polymer surface of the organic memory cell. Such process reduces number of masking steps performed. In addition, the process is scalable with lithographic wave length and can be performed on wide spread tool sets and photoresist material available in commercial market.

Abstract: This invention provides a method of depositing high-quality Si or SiGe epitaxial layers on SiGe substrates. By first depositing a thin Si seed layer on the SiGe substrate, the quality of the seed layer and of the subsequently deposited layers is greatly improved over what is obtained from depositing SiGe directly onto the SiGe substrate. Indeed, whereas the RMS surface roughness of the deposition of SiGe directly on SiGe, as measured by atomic-force microscopy (AFM), was 3–4 nm, it was more than an order of magnitude better when a thin Si seed layer was employed. This work was performed on an ultra-high-vacuum chemical vapor deposition (UHV/CVD) system; however, the same method would apply to other deposition systems such as atmospheric-pressure, low-pressure and rapid-thermal CVD.

Abstract: A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.

Abstract: The present invention provides, in one embodiment, a method (100) of forming dual work function metal gate electrodes in a semiconductor device. The method includes forming a gate dielectric (105) over a substrate (110) and depositing a mold layer (115) having a first opening (120) therein over the gate dielectric (105). The method further includes creating a first metal gate electrode (125) by depositing a first metal in the first opening (120). Other embodiments include an active device (200) produced by the above-described method and method of manufacturing an integrated circuit (300) using the above-described method.

Abstract: In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.

Abstract: A thin film made of an amorphous material having a supercooled liquid phase region is formed on a substrate. Then, the thin film is heated to a temperature within the supercooled liquid phase region and is deformed by its weight, mechanical external force, electrostatic external force or the like, thereby to form a thin film-structure. Thereafter, the thin film-structure is cooled down to room temperature, which results in the prevention of the thin film's deformation.

Abstract: A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses.

Abstract: A method of producing a semiconductor structure having at least one support substrate and an ultrathin layer. The method includes bonding a support substrate to a source substrate, detaching a useful layer along a zone of weakness to obtain an intermediate structure including at least the transferred useful layer and the support substrate, and treating the transferred useful layer to obtain an ultrathin layer on the support substrate. The source substrate includes a front face and a zone of weakness below the front face that defines the useful layer, and the useful layer is sufficiently thick to withstand heat treatments without forming defects therein so that it can be reduced in thickness to form the ultrathin layer. The resulting ultrathin layer is suitable for use in applications in the fields of electronics, optoelectronics or optics.

Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.