Abstract: A method for joining a silicon plate to a second plate, a laser beam being directed through the silicon plate at the second plate. In the process, the wavelength of the laser beam is selected in such a way that only a negligibly small amount of energy is absorbed in the silicon plate. A strongly absorbent material is hotmelted by the laser beam's energy and then produces a bond between the silicon plate and the second plate.

Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).

Abstract: A method of sharpening a tapered or pointed silicon structure, such as a silicon field emitter. The method includes oxidizing the silicon field emitter to form an oxide layer thereon and removing the oxide layer. Oxidizing occurs at a low temperature and forms a relatively thin (e.g., about 20 ? to about 40 ?) oxide layer on the silicon field emitter. The oxide layer may be removed by etching. The method may be employed to sharpen existing silicon structures or in fabricating tapered or pointed silicon structures. A silicon field emitter that has been sharpened or fabricated in accordance with the method is substantially free of crystalline defects and includes an emitter tip having a diameter as small as about 40 ? to about 20 ? or less.

Abstract: A lower barrier layer made of tantalum nitride having a thickness of approximately 25 nm is deposited by sputtering on a fourth insulating film inclusive of the sidewall surfaces and the bottom surfaces of a via hole and an upper-interconnect-forming groove. The sputtering is performed under the conditions where approximately 10 kW of DC source power is applied to a target. Thereafter, the DC source power is reduced to approximately 2 kW, and approximately 200 W of RF power is applied to a semiconductor substrate. Here, the lower barrier layer is subjected to a sputter-etching process employing argon gas at an etching amount of approximately 5 nm, so that a part of the lower barrier layer deposited on the bottom surface of the via hole is at least partially deposited on the lower part of the sidewall surface of the via hole.

Abstract: By placing the contact region for contacting row lines along a side parallel to the side having a column region for contacting row lines, the border of the LC device can be reduced because spacing relative to scribe and break lines is smaller.

Abstract: This invention discloses methods for the fabrication of organic semiconductor material-based devices under non-vacuum environment. In one embodiment, electrodes are formed by electrodeposition from an electrolyte containing ions or complexes of the electrode materials to be deposited. In another embodiment, electrodes are formed by solution processing from a solution (or ink) containing nano-particle of the electrode materials or the precursor of electrode materials to be deposited. In addition, two different modes, either layer by layer or layer to layer, are disclosed for the fabrication of organic semiconductor material-based devices, wherein all semiconductor organic materials required by the function of the desired device are deposited under an non-vacuum environment.

Abstract: A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-figure pattern made of simple figures is formed and a dummy pattern is formed using the simple-figure pattern. A gap that is not wider than a predetermined value is located in a final wiring pattern made of the wiring pattern and the dummy pattern is defined as an air gap region. Thus, an interconnection structure incorporating air gaps between wiring patterns is formed.

Abstract: The invention relates to a method for fabricating nanometer gate semiconductor device using thermally reflowed photoresist technology, comprising steps of (i) spin-coating two layers of photoresists on a substrate, where a bottom layer of photoresist is a polymeric photoresist having a lower sensitivity and a higher resolution, and a top layer of photoresist, is another polymeric photoresist having a higher sensitivity and a lower resolution, with respect to the electron beam; (ii) heating the photoresists for curing by way of using a hotplate; (iii) using photolithography in an electron beam direct writing manner to expose a pattern on the photoresists for forming a gate; (iv) using a developer and an etchant for developing and etching to form a recess on the gate; (v) plating a metallic layer on the recess of the gate using an electron gun evaporation technique; and (vi) removing the photoresists to obtain the gate, characterized in that after the etching of the recess of the gate, the photoresists are refl

Abstract: Methods for the deposition of tungsten films are provided. The methods include depositing a nucleation layer by alternatively adsorbing a tungsten precursor and a reducing gas on a substrate, and depositing a bulk layer of tungsten over the nucleation layer.

Abstract: The present invention includes integrated circuit packages, ball-grid array integrated circuit packages and methods of packaging an integrated circuit. One aspect of the present invention provides an integrated circuit package including a substrate having opposing first and second substrate surfaces and at least one electrical connection supported by the first substrate surface and adapted to couple with circuitry external of the package; a semiconductor die including circuitry electrically coupled with the at least one electrical connection; a first die surface coupled with the second substrate surface; a second die surface; and a cover coupled with the second die surface.

Abstract: An alignment mark section on a semiconductor substrate has two grooves which are filled with silicon oxide. The surface of the portion of the semiconductor substrate sandwiched by these grooves is lower than other portions of the semiconductor substrate to produce a step having a predetermined depth in the alignment mark section.

Abstract: A method of manufacturing the semiconductor chips comprises the steps of: pasting on a substrate an adhesive sheet having a property to retain its adhesive strength prior to a processing, then lose its adhesive strength after the processing; fixing a plurality of non-defective bare chips on this adhesive sheet, with their Al electrode pad surfaces facing down; coating a resin on a whole area other than the Al electrode pad surfaces of the plurality of non-defective bare chips including interspaces therebetween; applying a predetermined process to the adhesive sheet to weaken its adhesive strength of the adhesive sheet; peeling off a pseudo wafer bonding non-defective bare chips; and dicing the plurality of non-defective bare chips into a discrete non-defective electronic part by cutting the pseudo wafer at a position of the resin between respective non-defective bare chips.

Abstract: Disclosed is a method of manufacturing a semiconductor device. A monoatomic dopant having a high atomic weight is implanted to form an ion implantation layer, instead of using a dopant of a small atomic weight such as B or a molecular ion such as a BF2 in order to control the threshold voltage of the semiconductor device. Therefore, in an annealing process for mitigating damage caused by ion implantation, it is possible to limit TED (transient enhanced diffusion) of the dopant and prevent degradation of the film quality due to outgasing.

Abstract: After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 ?m or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.

Abstract: The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces.

Abstract: The present invention is directed to several inventive methods of monitoring anneal processes performed on implant regions, and a system for accomplishing same. In one aspect, the method comprises forming a first plurality of implant regions in a semiconducting substrate, performing at least one anneal process on implant regions, performing a scatterometric measurement of at least one of the implant regions after at least a portion of the anneal process is performed to determine a profile of the implant region and determining an effectiveness of the anneal process based upon the determined profile of the implant region. In other embodiments, one or more parameters of the anneal process may be varied on subsequently processed substrates based upon the determined efficiency of the anneal process.

Abstract: A method for forming a minute pattern includes forming a mask layer on an object being patterned. The mask layer is patterned to form a first mask pattern having a first width larger than a predetermined width. The first mask pattern is thermally treated to form a second mask pattern having a second width smaller than the first width. A polymer layer is formed on the second mask pattern. The polymer layer reacts with the second mask pattern to form a hardened layer on a boundary surface between the polymer layer and the second mask pattern, thereby forming a third mask pattern having a third width substantially identical to the predetermined width. The limits of the present photolithography equipment are overcome. Also, a semiconductor device having a CD of below about 100 nm is manufactured.

Abstract: A method of manufacturing an element having a microstructure of an excellent grating groove pattern or the like is obtained. This method of manufacturing an element having a microstructure comprises steps of forming a metal layer on a substrate, forming a dot column of concave portions on the surface of the metal layer and anodically oxidizing the surface of the metal layer formed with the dot column of concave portions while opposing this surface to a cathode surface thereby forming a metal oxide film having a grating groove pattern. When the interval between the concave portions of the dot column is reduced, therefore, a linear grating groove pattern having a large depth with a uniform groove width along the depth direction is easily formed in a self-organized manner.

Abstract: A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.

Abstract: A trench gate type field effect transistor capable of effectively suppressing the short channel effect is formed with a shallow junction between a source and a drain, at low resistance, and through a simple process. In a method of manufacturing a trench gate type field effect transistor (100A), wherein an impurity introduced layer (13) which is to become a source or a drain is formed by introducing an impurity into a semiconductor substrate (1), a trench (15) is formed in the impurity introduced layer, a gate insulating film (5) is formed on a bottom face of the trench (15), and a gate (G) is formed so as to fill the trench (15), laser annealing for activating the impurity is performed after the impurity is introduced into the semiconductor substrate (1) and before the gate G is formed.