Abstract: Embodiments of the invention provide a method of forming a chalcogenide material containing device, and particularly resistance variable memory elements. A stack of one or more layers is formed over a substrate. The stack includes a layer of chalcogenide material and a metal, e.g., silver, containing layer. A protective layer is formed over the stack. The protective layer blocks light, is conductive, and is etchable with the other layers of the stack. Further, the metal of the metal containing layer is substantially insoluble in the protective layer. The stack and the protective layer are then patterned and etched to form memory elements.

Abstract: A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a gate stack of the n-type transistor and a gate stack of the p-type transistor, which each have spacers which are surrounded with oxide. The method further involves etching a portion of the polysilicon from a gate of the p-type field effect transistor, depositing a low resistance material (e.g., Co, Ni, Ti, or other similar metals) on the n-type field effect transistor and the p-type field effect transistor, and heating the integrated circuit such that the deposited material reacts with the polysilicon of the n-type transistor and the polysilicon of the p-type transistor to form silicide.

Abstract: A trench device with collar oxide for isolation. A buried trench capacitor is formed in a lower portion of a deep trench in a substrate. A conductive layer, surrounded by a collar insulating layer and lower than the collar insulating layer, is deposited in an upper portion of the trench. The collar insulating layer lining the trench is partially removed to expose a portion of the surface of the substrate such that a portion of the conductive layer contacts the substrate. A buried strap is formed where the substrate contacts the conductive layer, as a single-side buried strap. The other portions of the conductive layer are isolated from the substrate by the collar insulating layer. Thus, conventional shallow trench isolation (STI) structure is omitted.

Abstract: A manufacturing method of a thin-film magnetic head with an MR element or a manufacturing method of an HGA with the head includes a step of forming a plurality of MR elements on a substrate or wafer, a step of forming a plurality of pairs of connection pads, each pair of connection pads being electrically connected across each MR element, a step of forming a plurality of thin-film short-circuit patterns on a surface of the wafer, each short-circuit electrically short-circuiting between each pair of connection pads, and a step of thereafter breaking each short-circuit pattern by laser radiation during a predetermined manufacturing process of the magnetic head.

Abstract: A method of forming a conductive pattern of a semiconductor device includes forming a conductive layer is on a substrate, forming a polishing protection layer on the substrate including over the conductive layer, and forming a step compensation layer on the polishing protection layer to reduce the step presented by the layer that is the polishing protection layer. The conductive layer is the exposed by removing select portions of the step compensation layer and the polishing protection layer. The conductive pattern is ultimately formed on the substrate by etching the exposed conductive layer. By planarization the intermediate structure several times once the step compensation layer is formed, a highly uniform conductive layer is sure to be formed.

Abstract: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.

Abstract: Ferroelectric memory devices can be formed by polishing an insulating layer on a plurality of ferroelectric capacitors with a silica slurry to reduce a height of the insulating layer above a surface of the plurality of ferroelectric capacitors so that the surface remains covered by a portion of the insulating layer. The insulating layer can be further polished with a ceria slurry to further reduce the height of the insulating layer and to expose a polishing stop layer on the surface of the plurality of ferroelectric capacitors. Related devices are also disclosed.

Abstract: A method of forming a sharp silicon structure, such as a silicon field emitter, includes oxidizing the silicon structure to form an oxide layer thereon, then removing the oxide layer. Oxidizing may occur at a low temperature and form a relatively thin (e.g., about 20 ? to about 40 ?) oxide layer on the silicon field emitter. The oxide layer may be removed by etching. A silicon field emitter that has been fabricated in accordance with the method is substantially free of crystalline defects and may include an emitter tip having a diameter as small as about 40 ? to about 20 ? or less.

Abstract: Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride-silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region.

Abstract: A method includes disposing a planarization layer on a surface of a layer of semiconductor material and disposing a lithography layer on a surface of the planarization layer. The method also includes performing nanolithography to remove at least a portion of the planarization layer, at least a portion of the lithography layer and at least a portion of the layer of semiconductor material, thereby forming a dielectric function in the surface of the layer of semiconductor material that varies spatially according to a pattern.

Abstract: Techniques for ball bonding wires in an integrated circuit are provided which allow formation of desired wire bond profile shapes for optimal performance. A wire is ball bonded to a first bond site in the integrated circuit with a bonding tool and at least one bend is formed in the wire. The wire is terminated at a second bond site with the bonding tool, thereby creating a wire bond profile. The technique is repeated for a plurality of additional wire bonds of the integrated circuit, and at least two wire bond profiles in the integrated circuit are substantially perpendicular to one another at a crossing point of the profiles.

Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

Abstract: Process for incorporating a back surface field into a silicon solar cell by depositing a layer of aluminium on the rear surface of the cell, sintering the aluminium at a temperature between 700 and 1000° C., exposing the cell to an atmosphere of a compound of Group V element and diffusing at a temperature of between 950 and 1000°C. so as to dope exposed p-type silicon surfaces with the Group V element. The step of exposing the cell to an atmosphere of a compound of a Group V element is carried separately from the step of sintering the aluminium layer, and subsequent to the step of depositing a layer of aluminium on the rear surface of the cell.

Abstract: There is provided a method for forming wiring or an electrode by coating a substrate with a composition comprising (A) a complex of an amine compound and a hydrogenated aluminum compound and (B) a titanium compound or a composition comprising the complex and (C) metal particles and subjecting the obtained coating film to heating and/or a light treatment. By the method, a film can be formed that uses a conductive film forming composition with which wiring and an electrode that can be suitably used for electronic devices can be formed easily and inexpensively.

Abstract: A contact structure and manufacturing method thereof is provided. A substrate having a first conductive layer and a dielectric layer thereon is provided. The dielectric layer has a contact opening that exposes a portion of the first conductive layer. A conductive nano-particle layer is formed on the exposed surface of the first conductive layer. Thereafter, a second conductive layer is formed inside the contact opening to cover the conductive nano-particle layer and form a contact structure. The conductive nano-particle layer at the bottom of the contact prevents the second conductive layer from peeling off and costs much less to produce.

Abstract: A praseodymium (Pr) gate oxide and method of fabricating same that produces a high-quality and ultra-thin equivalent oxide thickness as compared to conventional SiO2 gate oxides are provided. The Pr gate oxide is thermodynamically stable so that the oxide reacts minimally with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit a Pr layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: A method of forming a CMOS transistor on a substrate is provided, wherein the method requires only two implanting procedures to form all source/drain and light doped region. First, the source/drain of an NMOS transistor is formed by using a photoresist layer which covers up the source/drain of a PMOS transistor as a mask with a phosphorus dopant being implanted into. Next, the lightly doped region of an NMOS transistor and the source/drain of a PMOS transistor are formed by using a photoresist layer which covers up the source/drain of an NMOS transistor as well as the gate as masks with a boron dopant being implanted into. Of which, the dosage of the boron dopant is smaller than that of the phosphorus dopant.

Abstract: A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT). First, active layers of a N type LTPS TFT (NLTPS TFT) and a P type LTPS TFT (PLTPS TFT) are formed on a substrate, and a gate insulating (GI) layer is formed on the substrate. Then, a source electrode, a drain electrode, and lightly doped drains (LDD) of the NLTPS TFT are formed. Further, gate electrodes of the NLTPS TFT and the PLTPS TFT are formed on the gate insulating layer. Finally, the gate electrode of the PLTPS TFT is utilized to form a source electrode and a drain electrode in the active layer of the PLTPS TFT.

Abstract: A porous dielectric film for use in electronic devices is disclosed that is formed by removal of soluble nano phase porogens. A silicon based dielectric film having soluble porogens dispersed therein is prepared by chemical vapor deposition (CVD) or by spin on glass (S.O.G.). Examples of preferable porogens include compounds such as germanium oxide (GeO2) and boron oxide (B2O3). Hot water can be used in processing to wet etch the film, thereby removing the porogens and providing the porous dielectric film. The silicon based dielectric film may be a carbon doped silicon oxide in order to further reduce the dielectric constant of the film. Additionally, the porous dielectric film may be treated by an electron beam to enhance the electrical and mechanical properties of the film.