Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element configured to be changed in a resistance value according to a value of data stored therein; a first reference resistance element having a first resistance value; a second reference resistance element having a second resistance value larger than the first resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and fourth input termi

Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.

Abstract: A modular interconnectivity assembly for interconnecting elements of a point of sale system, the modular interconnectivity assembly including at least one interconnectivity module including an Input/Output (I/O) hub having at least one upstream facing port and at least two downstream facing ports, at least one upstream connector connected to the at least one upstream facing port of the (I/O) hub and adapted for communication in accordance with a first communication protocol, at least one downstream connector connected to at least one of the at least two downstream facing ports and adapted for communication in accordance with the first communication protocol and at least one interface connected to another of the at least two downstream facing ports and adapted for communication in accordance with a second communication protocol, different from the first communication protocol.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: Examples disclosed herein provide a computing assembly. The computing assembly includes a first CPU package mounted on a PCB, and a second CPU package mounted on the PCB. The computing assembly includes a connector to bridge a convection between a connection interface of the first CPU package and a connection interface of the second CPU package, wherein the connector comprises a plurality of signal paths for routing signals from the first and second CPU packages. The signals paths include a first signal path to route signals between the first and second CPU packages, and a second signal path to route signals between the first CPU package and another component.

Abstract: A method and system for sharing content, by which an experience is shared between users in real-time based on an interactive service between devices is provided. The method includes: receiving content-related information from at least one peripheral device reproducing content to be shared while an interactive service is being provided; and transmitting the content-related information to at least one second communication device connected to a first communication device by the interactive service based on the received content-related information.

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract: A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.

Abstract: A configurable multi-protocol transceiver implemented in an integrated circuit (“IC”) includes configurable deskew circuitry. The transceiver has various configurable deskew settings to facilitate effectively adapting transmit and/or receive communications corresponding to a selected one of a plurality of high-speed communication protocols and/or adapt to different implementations in which a deskew block addresses either just static skew or both static and dynamic skew. Configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. Configurable circuitry is adapted to control a deskew character transmit insertion frequency. A programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition.

Abstract: An information handling system includes a host processing complex and a wireless management system. The host processing complex instantiates a hosted processing environment and includes a first general-purpose processing unit (GPU) and a GPU hot-plug module that enables a hot-plug operation to replace the first GPU with a second GPU while power is provided to the host processing complex. The hosted processing environment instantiates a first workload on the first GPU. The wireless management system operates out of band from the hosted processing environment, directs the hosted processing environment to halt the first workload, and directs the GPU hot-plug module to perform the hot-plug operation.

Abstract: A method and apparatus are provided for controlling data flow by storing variable length encoded information bits in a circular buffer in a write operation to a virtual write address comprising a first wrap bit value appended by a current write address within the buffer address range and generating an interrupt alarm if the virtual write address crosses a virtual alarm address comprising a second wrap bit value appended by an alarm address within the buffer address range, where the first and second wrap bit values each toggle between first and second values every time the current write address or alarm address, respectively, wraps around the circular buffer, thereby synchronizing data flow in the circular buffer and/or preventing buffer overflow.

Abstract: A system and a method for supporting a hierarchical connection of an accessory apparatus to a terminal and other accessory apparatuses are provided. The accessory apparatus includes a terminal connection interface connecting to a terminal, at least one connection interface connecting at least one other accessory apparatus, and an apparatus controller setting and controlling the terminal to identify a resistance value corresponding to a particular accessory apparatus according to whether the at least one other accessory apparatus is connected.

Abstract: A method is implemented by a network device to configure the operation of a Peripheral Component Interconnect Express (PCIe) switch to enable an efficient transition from a first active processor in a first root complex to a backup processor in a second root complex. The method involves determining the first active processor in the first root complex and a set of backup processors and a set of root complexes, and configuring each root complex for independent PCIe switch communication. The method further includes detecting a failure of the active processor in the first root complex, selecting and notifying the backup processor and the second root complex to transition to be a second active processor and second root complex, and starting communication with PCIe devices using previously configured independent PCIe switch communication for the second processor of the second root complex.

Abstract: A real-time data management system for accessing data in a power grid that controls a transmission delay of real-time data delivered via a real-time bus, and delivers real-time data in a power grid. A unified data model covering various organizations and various data resource may be included. Multi-bus collaboration and bus performance optimization approaches may be used to improve efficiency and performance of the buses. An event integration and complex event process component may be included to provide status of the power grid. A high volume of real-time data and events may be managed to provide data transmission with a low latency, provide flexible extension of the number of data clusters and the number of databases to ensure high volume data storage, and achieve a high speed and transparent data access. Additionally, rapid design and development of analytical applications, and the near real-time enterprise decision-making may be enabled.

Abstract: A plurality of devices communicate over a bus, the devices comprising a plurality of controller devices and a plurality of second devices. Each of the controller devices is responsible for assigning one or more of the addresses including at least the address of each of a respective one or more of the second devices. A controller device comprises address allocation logic configured to assign an address to each of that controller device's respective one or more second devices, by: searching for a currently unassigned address to assign to each of the respective one or more second devices, and if an unassigned address for one of those one or more second devices cannot be found, to issue a request to at least one other of the controller devices requesting that the other controller device changes one of the one or more addresses which that other controller device is responsible for assigning.

Abstract: A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.

Abstract: Methods and apparatuses for offloading functionality in an integrated circuit are presented. Certain embodiments are described that disclose methods pertaining to implementation of a universal offload engine that can service several functional blocks, each configured to perform a different function. The offload engine can be iteratively implemented with a common interface to functional blocks. Work descriptors can be used between DMA engines and corresponding functional blocks to instruct the DMA engines how to transport data between memory locations and/or to reformat the data.

Abstract: Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field broadband bus architecture system including a bus controller and at least one bus terminal, the bus controller is connected with the bus terminal over a two-wire data transfer network, and the method includes steps of: electing one of the bus controller and the bus terminal as a best master clock; determining whether an IP address of the device of the best master clock is the same as an IP address of the bus controller; if so, then determining the bus controller as a master device of clock synchronization, and transmitting by the bus controller a synchronization message to the bus terminal for clock synchronization; and otherwise, returning to the step of electing one of the bus controller and the bus terminal as the best master clock.

Abstract: A storage node includes a storage element module. The module includes a first peripheral component interconnect express (PCIe) switch suitable for uplink connection, a second PCIe switch coupled to the first PCIe switch, and at least one connection element coupled to the second PCIe switch, suitable for coupling with at least one storage element. All PCIe end point elements and uplink connection elements are in a PCIe card form factor as defined in PCI Express Card Electromechanical Specification.

Abstract: The invention discloses a method for implementing a real-time industrial internet field broadband bus, the method including: determining, by a bus controller, the number of bus terminals connected therewith; and allocating, by the bus controller, time slices for the bus terminals according to the number of bus terminals, and transmitting, by the bus controller, the time slices to the bus terminals so that the bus terminals operate in the allocated time slices. Moreover data are transmitted in the bus system by removing Ethernet/IP message header information to thereby reduce the length of the message, and shorten a transmission delay and a bus scan periodicity so as to improve the real-time characteristic of the bus system.