Abstract: A method and a system embodying the method for data lockdown and data overlay in a packet to be transmitted, comprising providing a first and a second masks comprising one or more position(s) and a data value at each of the one or more position(s); aligning the masks with the packet; comparing the data value at each of the one or more position(s) in the first mask with the data value at the one or more aligned position(s) in the packet; optionally replacing a data value at each of the one or more position(s) in the packet with a data value at the one or more aligned position(s) in the second mask; and providing the packet for transmission if the data value at each of the one or more position(s) in the first mask and the data value at the one or more aligned position(s) in the packet agree.

Abstract: A transmission apparatus includes a logic circuit for performing a predetermined process, and outputting a logic output signal depending on the process, an open-drain signal generation circuit, connectable at an input terminal to the logic circuit and at an output terminal to a pull-up resistor, and a transmission path failure determination circuit for determining whether there is a failure in a transmission path which transmits a signal outputted from the logic circuit via the open-drain signal generation circuit, wherein the transmission path failure determination circuit includes an edge waveform information obtaining circuit for obtaining edge waveform information indicating a waveform of at least one of a rising edge and a falling edge of an application signal, and a failure determination circuit for determining whether the edge waveform information satisfies a predetermined condition, and outputting a failure signal indicating that there is a failure in the transmission path.

Abstract: Upon receiving a request (203) in an initiator interface protocol identifying information to be returned in-order, an integrated circuit protocol bridge circuit device (200) allocates, to the ordered request, entries in a first ordered queue (e.g., 211) and a first static queue (e.g., 213) for the initiator interface protocol, generates a plurality of split target requests in a target interface protocol from the ordered request, and allocates the plurality of split target requests to entries in a second ordered queue (e.g., 217) and a second static queue (e.g., 218) for the target interface protocol, so that, upon receiving a plurality of out-of-order target responses, an allocated entry in the first ordered queue (211) for the first ordered initiator request is deleted only after a plurality of counter fields in the first static queue indicate that target responses have been received for all of the plurality of split target requests.

Abstract: Methods and systems for generating interrupts are provided. One method includes maintaining an in-pointer array by a response direct memory access (DMA) module of an adapter indicating that a message has been posted at a host memory of a host system coupled to the adapter for sending and receiving data using a network; updating an out-pointer array at the response DMA module by a host system processor, after the host system processor reads the message posted at the host memory; receiving event information by a hardware based, interrupt module of the response DMA module, the interrupt module using the event information and information stored at an interrupt array to determine that an interrupt is to be generated for the host processor; and generating the interrupt for the host processor by the interrupt module, without using an adapter processor.

Abstract: A delay control device, a delay control method and an electronic apparatus are provided. The delay control device includes: a trigger port, configured to receive a trigger signal; a first interface; a second interface; a control module, configured to disconnect connection between the first interface and the second interface in response to a case that the trigger port receives the trigger signal; and a timing module, configured to carry out timing for a duration; the control module is further configured to connect the first interface and the second interface in response to a case that the timing module completes timing of the duration. The delay control device can achieve a delay control function, prevent program confusion, improve efficiency and save cost.

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: A system on chip includes a display serial interface (DSI) which includes a PHY protocol interface (PPI) used for communication between a DSI host controller and a D-PHY. The DSI host controller includes a register configured to store first indicator data indicating a PPI packetizing method and a lane distributor configured to determine a size of a symbol to be transmitted to the PPI and an order of first processing units to be included in the symbol based on the first indicator data.

Abstract: An apparatus, a method, and an electronic device for implementing SSD (solid-state drive) data interactions are provided. The apparatus for implementing the SSD data interactions comprising a master controller, a detector, and a retimer coupled between an SSD and a CPU (central processing unit) for: performing signal enhancement processing on information transmitted between the SSD and the CPU; and monitoring a connection status of a data port corresponding to the SSD and send a monitoring result to the CPU.

Abstract: A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.

Abstract: A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is connected, in a first period of quiescing of I/O operations in the embedded port. The driver transmits one or more commands to the embedded port to resume selected I/O operations in the embedded port. A reinitialization of the driver is performed during a second period of quiescing of I/O operations in the embedded port, prior to sending a command to allow normal I/O operations in the embedded port.

Abstract: An example electronic device may include a peripheral component interconnect express (PCIe) connector that includes a number of lane ports that may be arranged in a row. Physical lane numbers of the lane ports in a first half of the row may be in either an ascending order or a descending order from a first end of the row toward a middle of the row. Physical lane numbers of the lane ports in a second half of the row may be in either a descending order or an ascending order from the middle of the row toward a second end of the row. The order of the second half may be ascending when the order of the first half is descending, and the order of the second half may be descending when the order of the first half is ascending.

Abstract: An embedded port of a host bus adapter of a storage controller receives, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations. One or more commands are received to resume selected I/O operations in the embedded port. A second set of commands is received to quiesce I/O operations for a second period. A command is received to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations.

Abstract: Forwarding devices and corresponding methods are provided in which a plurality of input data streams are distributed among a plurality of output data streams on the basis of synchronization marking. One example method of forwarding data includes receiving a plurality of input data streams, where at least some of the input data streams include synchronization markers indicating which data of the input data streams are to be output synchronously, in one or more common time segments. Further included in the method is distributing the data to be output synchronously among a plurality of output data streams on the basis of the synchronization markers. The distributing is carried out in such a way that data which, according to the synchronization markers, are to be transmitted in a common time segment are provided in the same time segment in all the output data streams to which the data are to be assigned.

Abstract: One embodiment provides an electronic control unit (ECU) for a vehicle. The ECU includes transceiver circuitry, voltage measurement circuitry and feature set circuitry. The transceiver circuitry is to at least one of send and/or receive a message. The voltage measurement circuitry is to determine at least one of a high bus line voltage (VCANH) value and/or a low bus line voltage (VCANL) value, for each zero bit of at least one zero bit of a received message. The received the message includes a plurality of bits. The feature set circuitry is to determine a value of at least one feature of a feature set based, at least in part, on at least one of a high acknowledge (ACK) threshold voltage (VthH) and/or a low ACK threshold voltage (VthL). The feature set includes at least one of an operating most frequently measured VCANH value (VfreqH2) of a number of VCANH values and/or an operating most frequently measured VCANL value (VfreqL2) of a number of VCANL values.

Abstract: An industrial controller that controls operation of an industrial system. The industrial controller comprises a processor and a memory storing instruction, wherein the instructions cause the processor to perform certain functions. In particular, the instructions cause the processor to communicate high speed data in a first industrial protocol between the industrial controller and a high speed device during a first frame section but not during a second frame section of a controller frame of the industrial controller and communicate linking device data in a second industrial protocol between the industrial controller and a linking device during the second frame section but not during the first frame section or during the third frame section of the controller frame.

Abstract: Methods and apparatus for reducing accelerator-memory access costs in platforms with multiple memory channels. The apparatus includes a computing platform having multiple accelerators and multiple memory devices accessed via a plurality of memory channels. Jobs are submitted via software running on the computing platform to access a function to be offloaded to an accelerator. Under the offloaded function, the accelerator accesses one or more buffers that collectively requiring access via multiple memory channels among the plurality of memory channels. Accelerators having an available instance of the function are identified, and an aggregate cost for accessing the one or more buffers via the multiple memory channels are calculated for each of the accelerators. The accelerator with the least aggregate cost is then selected to offload the function to. New Instruction Set Architecture (ISA) instructions are also disclosed to identify memory pages and memory channels used for buffers.

Abstract: A transmitter comprising an input data buffer to store a plurality of bytes received on a first interconnect; multiplexer circuitry coupled to the input data buffer; and an output buffer coupled to the multiplexer circuitry, a second interconnect, and a third interconnect. The multiplexer circuitry is to: receive byte enable information in the input data buffer; determine that one or more of the plurality of bytes stored in the input data buffer are invalid; store an indicator in the output buffer; store valid bytes of the plurality of bytes in the output buffer to transmit on the third interconnect; and store the byte enable information in the output buffer to transmit on the third interconnect.

Abstract: An apparatus for combining trace data from a plurality of trace sources has an input interface to receive the trace data, and an output interface to output a trace stream. A network of interconnected funnel elements combines the trace data to produce the trace stream. Each funnel element has an output port and a plurality of input ports arranged to receive trace data either from one of the trace sources, or from an output port of another funnel element in the network, and associated control circuitry to control connection of the input ports to the output port. The control circuitry determines control data indicative of a number of trace sources whose trace data is to be routed through each of the input ports of said funnel element, and controls the timing allocation of the associated funnel element's output port to each input port in dependence on the control data.

Abstract: Systems and methods described herein reduce contention on shared buses through which multiple sensors send sensor readings to a computing destination by allowing different query rates for each sensor and dynamically adjusting the query rate for each sensor based on the readings that sensor reports. A first query is sent to a sensor via a bus to request a current sensor reading from the sensor. In response to the first query, the sensor sends the current sensor reading via a bus. A function of the current sensor reading, a predefined time range, and a predefined reading-value range is evaluated to determine a time interval between the first query and a second query to be sent to the sensor. When the amount of time elapsed since the first query was sent matches the time interval, the second query is sent to the sensor via the bus to request an updated sensor reading.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.