Abstract: A digital photodetector circuit having a photosensing stage connected to a depletion mode field effect transistor forming an inverter stage, increased sensitivity is achieved by then coupling the output of the photo inverter to a second photo inverter whose photosensitive element serves as the active load of an enhancement mode field effect transistor in the inverter stage. The circuit is readily fabricated in integrated structures. The circuit performance may be adjusted for responsiveness to light sensitivity and to provide selectable electrical output signal level and impedance matching including bistable performance.

Abstract: A MIS device including a substrate bias generating circuit comprising: an oscillating circuit for generating clock signals; a pumping circuit comprised of a charging and discharging circuit and a bias circuit, for absorbing charges in a semiconductor substrate, and; a clamp circuit for clamping the potential of the substrate at a desired level.

Abstract: A device is described for modifying the charging behavior of a charge storage device, such as a capacitor, so that the device charges substantially in accordance with a square law function responsively to a linear charging input current. The device has particular utility in a signal-conditioning system of the type including an averaging detector, a gain stage and a charge storage device coupled between the output of said detector and the input of said gain stage so that the input to said gain stage behaves in a similar manner to the output of an RMS detector.

Abstract: A power field-effect switching transistor is switched-on by charging its gate-source capacitance by connecting a capacitor thereto by means of a first transistor. Switching-off of the power field-effect switching transistor is achieved by discharging the gate-source capacitance by switching-on a second transistor. In this manner, the charging and discharging processes take place at low resistance, and therefore in a short period of time. As a result, switching times and switching power losses for the power field-effect switching transistor are minimized. In addition, the need for a separate auxiliary voltage source and inductive circuit elements is obviated.

Abstract: An MOS FET inverter driver circuit. A first FET of the depletion type, a resistance formed by a depletion type FET having its gate connected to its drain, and a second FET of the enhancement type are connected in series between a positive voltage source and ground. Third and fourth FET's both of the enhancement type are also connected in series between the voltage source and ground. The gates of the first, second, and fourth FET's are connected directly to an input terminal. The gate of the third FET is connected to the juncture of the resistance FET and the second FET. A capacitance is connected between the juncture of the resistance FET and the first FET and the juncture of the third and fourth FET's, an output terminal is also connected to this juncture. The circuit obtains bootstrap action by virtue of the capacitance to provide high voltage drive to turn the third FET, the output pull-up transistor, on.

Abstract: A magnet is bonded to a skewed-hysteresis Hall switch in such a position that the magnetic flux, normal to the Hall element, is equal to the average of the magnetic flux required to operate and the magnetic flux required to release the Hall switch. This magnet-Hall-switch assembly is made by initially employing a magnet of much greater strength than needed. The Hall switch is energized and subjected to an oscillating field of zero average value. The on-time to off-time ratio of the magnet-Hall-switch assembly is measured. A demagnetizing field is adjusted to a strength that is directly related to the difference between unity and the Hall switch on-to-off time, and the magnet is then subjected to the adjusted demagnetizing field. These steps are repeated several times. The magnet is thus partially demagnetized to import to the magnet-biased Hall switch a symmetrical hysteresis characteristic.

Abstract: A phase locked-loop circuit includes a non-linear voltage controlled oscillator ideally producing a desired output frequency as a function of time and a memory producing signals which add to the phase locked-loop phase error feedback signal to correct for the VCO non-linearities. A calibration circuit upon activation is responsive to the phase error feedback signal for altering the contents of the memory such as to reduce or eliminate the phase error.

Abstract: This disclosure relates to a variable pulsewidth gated clock generator which is able to provide output clock signals with the same rise rate as an external driving clock with the output signal being varied in duration according to logic conditions within the integrated circuit. The circuit of the present invention as disclosed includes a latch which is set by the first phase of a two-phase clock to set the internal logic of the circuit to generate a large output signal during the second phase of the two-phase clock.

Abstract: Integrable semiconductor circuit, including a negatively fed-back non-inverting operational amplifier, a first resistor connected between the signal output and the inverting input of the amplifier, a second resistor connected to the inverting input, first and second capacitors, the second capacitor being connected between the second resistor and reference potential, forming a voltage divider including the first and second resistors and the second capacitor connected between reference potential and the output of the amplifier with a first circuit point disposed between the second resistor and the second capacitor connecting the inverting input of the operational amplifier to reference potential, an operating potential source connected to one of the supply inputs of the amplifier and the other supply input being connected to reference potential together supplying the amplifier with a supply voltage, series-connected resistors having a second circuit point disposed therebetween, the resistors being connected bet

Abstract: A photodiode receiver circuit having self-contained automatic gain control and which is temperature compensated over a wide operating range contains a resistor coupled in series between a bias power supply and one end of an avalanche photodiode. Self-generated AGC action results from the fact that the gain of an avalanche photodiode increases as the bias voltage applied across the diode increases. As the light intensity received by the diode increases, there is a corresponding increase in the current flow through the diode and the series-connected resistor. The consequential increase in IR drop across the resistor decreases the bias voltage across the diode, so that the gain of the diode is reduced. Through this action, the dynamic range of optical input of the photodiode will be increased for a fixed dynamic range of electrical output.Temperature compensation is achieved by coupling a temperature-sensitive voltage divider circuit between the bias voltage supply and the gain-controlling resistor.

Abstract: A solid state relay employing MOSFET power switching devices is disclosed. A d-c output relay is disclosed using a single power MOSFET device and an a-c output relay is disclosed employing series opposition power MOSFETS.

Abstract: A line driver circuit for driving a unit located a long distance away through a long transmission line, comprising an output stage having an emitter follower including transistors in which an output-stage transistor provides an output signal of a high potential or a low potential in response to the electric potential of an input signal. A discharge pass is connected to the base of the output-stage transistor, for drawing charges on the base of the output-stage transistor off thereof and thus shortening the fall time of the output waveform.

Abstract: Push-pull driver with reduced noise generation resulting from driver switching. A further transistor is arranged between the driver output transistor (which becomes conductive at the low output level) and the chip ground line. Its base is connected to a reference voltage source the other pole of which is connected to the ground plane of the circuit card to which the corresponding semiconductor chip is attached. If a noise voltage is generated on the chip ground line, the emitter potential of the further transistor is pulled up. As its base potential is maintained at a fixed value by the applied reference potential, this transistor becomes less conductive. As a result, the rate of current change in the output stage is reduced. The slowed down current rise, leads to a reduced noise voltage developing on the common chip ground line.

Abstract: A current source circuit includes a current mirror circuit having a master transistor and at least one slave transistor. The master transistor is coupled to a differential amplifier. The differential amplifier includes a pair of transistors, one thereof being coupled to a reference current source and the master transistor and the other one having a collector electrode connected to the base electrodes of the master and slave transistors for producing a current through the collector electrode substantially equal to the total current flow through the base electrodes of the master and slave transistors.

Abstract: An in-phase voltage elimination circuit in which a Hall element has first and second control current input terminals and first and second output terminals, the first and second control current input terminals fed with a control current and the first output terminal connected to one input terminal of an operational amplifier. The other output of the operational amplifier is connected to ground, and the output terminal of the operational amplifier is connected to one of the first and second control current input terminals. A Hall output is produced at the second output terminal of the Hall element.

Abstract: A log-conformance correction circuit for a prototype circuit employing semiconductor devices comprises a quad of devices with voltage drops arranged in series, and currents or current densities driven such that the logarithmic components in the voltage drops sum to zero while log-conformance error components are produced. A correction quad suitably may comprise two pairs of semiconductor devices in which the current densities in one pair are cross-proportional with the current densities of the other pair, and of a different magnitude to establish a current density ratio between the pairs. The log-conformance error components which are generated by the correction quad are inserted into the prototype circuit to cancel log-conformance error therefrom.

Abstract: An improved multiplier circuit of the type including an input operational amplifier and a gain cell is disclosed. The gain cell is connected to the amplifier such that a first signal can be generated in response to and as a logarithmic function of an input signal, a control signal can be added to the first signal and a second signal can be algebraically generated as an antilogarithmic function of the algebraic sum of the first and control signals. The improvement includes means for providing a correcting signal as a function of the control signal at the output of the input amplifier substantially equal and opposite to signals produced at the output of the input amplifier by changes in the control signal.

Abstract: A signal generator which may be fabricated as monolithic integrated circuit is disclosed. The signal generator includes a counter having a plurality of stages and providing parallel outputs and a plurality of flip-flops. A programmable logic array capable of functioning as AND and OR logic and composed of a matrix arrangement of programmable elements receives as inputs the parallel outputs of the counter and provides inputs to the flip-flops to generate signals at the outputs of the flip-flops.

Abstract: A MOS time delay circuit including a MOS regulated voltage supply circuit for supplying a voltage proportional to a predetermined trigger voltage and a RC delay circuit having a first input connected to the regulated voltage supply circuit, and a second input connected to the signal input, and an output. The circuit also includes a variable trigger point inverter having an input connected to the output of the RC delay circuit, and signal output.

Abstract: A semiconductor circuit consisting of a dynamic-type circuit and a bias-voltage generating circuit. The bias-voltage generating circuit is comprised of a first bias-voltage generator and a second bias-voltage generator. The first generator absorbs a variable substrate current, the magnitude of which is proportional to the operating frequency of the dynamic-type circuit, while the second generator absorbs a substrate current, the magnitude of which is not proportional to the operating frequency of the dynamic-type circuit. Alternately, both portions of the substrate current may be absorbed via the same circuitry.