Abstract: Electronic switch for switching electrical signals, comprising an input buffer (1) of the open collector type of which the input is connected to the control input (2) of the switch. The output of said input buffer is connected to (1) the input of an output buffer (3) which the output is connected to the signal output (8) of the switch, (2) a diode (4) of which the other electrode is connected to the signal input of the switch and (3) a load resistance (5). Furthermore the other terminal of said load resistance is connected to the signal input of the switch.

Abstract: Bipolar inputs are afforded by the plus inputs of first and second differential input amplifiers. A first gain determining resister is connected between the minus inputs of the differential amplifiers. First and second diodes are connected between the respective minus inputs and the respective outputs of the differential amplifiers. First and second FETs have their gates connected to the outputs of the amplifiers, while their respective source and drain circuits are connected between the respective minus inputs and an output lead extending to a load resister. The output current through the load resister is proportional to the absolute value of the input voltage difference between the bipolar input terminals. A third differential amplifier has its plus input terminal connected to the load resister. A second gain determining resister is connected between the minus input of the third differential amplifier and a voltage source. A third FET has its gate connected to the output of the third amplifier.

Abstract: A generating circuit for producing a linear ramp output voltage comprises an electronic switch and a ramp circuit connected to the electronic switch. The ramp circuit includes a single active component having first and second input terminals and an output terminal. The ramp circuit has positive and negative feedback to the input terminals of the active component.

Abstract: A fast-operating, minimally complex circuit for automatically clamping the P wells of a CMOS integrated circuit to the most negative potential of the overall circuit. Each of a plurality of N-channel control transistors has its drain connected to a respective one of the circuit nodes whose potential may be the most negative at any given time. The source terminals of all of the control transistors are coupled to a common negative supply bus which is connected to all of the P wells in the integrated circuit. The gates of all of the control transistors are held at a potential which causes them to conduct drain-to-source current. If one of the nodes suddenly drops in potential, the respective control transistor conducts a current in the reverse direction which lowers the potential of the common bus to approximately the potential of the respective node. The respective control transistor conducts heavily until the common bus is thus clamped, and then conducts just enough current to maintain the clamping.

Abstract: A "H" switching circuit for providing current drive to a load coupled between first and second outputs thereof comprising first and second paired switching transistor circuits each including an upper transistor that is cross-coupled at the first and second outputs to a respective paired lower transistor. The respective pairs of switching transistors are alternately rendered conductive whereby the polarity of the load current drive may be reversed. First and second transistors are provided with each being coupled respectively between a lower transistor of one of the paired switching transistor circuits and the upper transistors of the other one of the paired switching transistor circuits for severely limiting current spikes that otherwise occur during switching at the outputs of the switching circuit.

Abstract: Disclosed is a frequency converter circuitry having square-law transfer characteristics.In order to reduce undesirable harmonic components of the output signal, the circuitry comprises a plurality of active elements, each being responsive to respective harmonic components and having a characteristic adjusting means, connected in parallel with each other so as to provide an overall input/output transfer function approximating a square-law transfer characteristic.

Abstract: The present invention relates to a single-ended push-pull type inverter. Such inverter in the prior art generated a large through-current flowing through series-connected output transistors. This large through-current caused not only a large power consumption but also an instability of the entire circuit including the inverter. The present invention improves these disadvantages by inserting a phase inverter stage having a current regulating function just before the output transistors and includes a first transistor having a base receiving an input signal, the phase inverter stage having an input end connected to the collector of the first transistor, a second and a third transistor connected in series, the bases of the second and third transistors being electrically connected, respectively, to the collector of the first transistor and output end of the phase inverter stage and an output terminal connected to the circuit portion connecting the second and third transistors.

Abstract: A circuit for driving a power transistor that forms a part of an inverter circuit used in motor control in which the circuit is switched at high voltages. The motor drive circuit isolates and amplifies a control signal so as to operate the power switching transistors. The base drive circuit employs two characteristics of power transistors to derive maximum protection and maximum performance simultaneously. This control is accomplished by sensing both the collector-to-emitter voltage of the power transistor as well as the base-to-emitter voltage thereof. In an alternate embodiment described herein, a feedback circuit is also provided sensitive to collector-to-emitter voltage for shortening the try-time associated with the power transistor.

Abstract: A square root circuit is provided with a high gain amplifier for receiving the input and a squaring circuit in the negative feedback circuit of the amplifier to produce the desired square root output. A second negative feedback path is provided with a feedback resistor and switching means for selectively completing the connection of the second feedback path when the amplifier input falls below a certain predetermined level so that the amplifier provides a linear response in the low input region. This linear response will make the accurate setting of the zero possible without any manual switching in the amplifier feedback.

Abstract: A function generator includes an operating voltage source, a capacitor, a first resistor coupled to the capacitor so that the capacitor charges through the first resistor, a second resistor coupled to the capacitor to discharge the capacitor through the second resistor, a third resistor, and an operational amplifier for selectively coupling the third resistor to the capacitor to discharge the capacitor through the third resistor selectively in parallel with the second resistor to alter the discharging time constant of the function generator.

Abstract: A semiconductor resistor element comprising a semiconductor film which has a desired shape and electrode wirings at both ends thereof, and a control electrode provided between the two ends of the semiconductor film via an insulating film. The control electrode is served with a control voltage which controls the resistance of the semiconductor film. Namely, the control electrode is served with a control voltage that changes with the change in temperature to offset the change in resistance of the semi-conductor film caused by the change in temperature.

Abstract: A delay signal generating circuit includes feedback loops and components for selectively setting the delay time of a delay unit in one of the loops. The circuit can be used to provide an adjustable delay to a signal being propagated therethrough, and the delay unit can be bypassed.

Abstract: Circuit and method for generating a ramp signal having an incrementally changing slope. The invention is particularly useful for ramping magnetic recording bias or erase signals by providing a relatively slow slope within the non-linear region of the magnetic medium characteristic while providing a relatively steep slope in the linear region to reduce recording of disturbing "pop" signals.

Abstract: A rectifier circuit includes three operational amplifiers, the first of which is provided with feedback loops containing diodes of opposite polarity. The other op-amps are coupled to the output of the first one via the respective diodes, and the outputs thereof are fed back to the inputs thereof and to the input of the input op-amp.

Abstract: A pulse stretching integrated circuit includes an on-chip capacitor. A first transistor means including an input transistor and an emitter follower transistor supplies a charging current to the capacitor so as to charge it to a first voltage when an input signal pulse is in a first logical state. A differential transistor pair has a first input coupled to the emitter follower transistor and to the capacitor and has a second input coupled to a reference voltage for generating a first output when the capacitor voltage is less than the reference voltage and for generating a second output when the capacitive voltage is greater than the reference voltage. An additional transistor is coupled to the capacitor for discharging the capacitor when the input signal pulse is in a second logical state causing the voltage at the first input of the differential pair to fall below the reference voltage.

Abstract: A pair of voltage followers, having offsets which differ by a fraction of the threshold voltage of a diode, are coupled to respective sources of signal and load voltage to provide unequally offset ouput voltages. An amplifier, coupled to the voltage followers, provides an output current when the difference of the signal and load voltages is of a given sense and magnitude, the output current being substantially zero otherwise.

Abstract: A static load for a high voltage driver includes first and second depletion mode field effect transistors and a diode-connected enhancement mode field effect transistor. The static load is arranged with a switching transistor to form a high voltage driver circuit. When the output of the driver circuit is at a relatively low potential, current drawn from the high voltage power supply is substantially reduced by applying a source to gate potential through the diode-connected transistor to one of the depletion mode transistors below the threshold voltage of the depletion mode transistor.

Abstract: A synchronized delay line is described which is tapped to provide a plurality of timing signals. The delay line is insensitive to voltage changes, temperature changes and wafer processing variations. It is ideally suited for providing on-chip timing signals derived from a reference clock for MOS integrated circuits.

Abstract: A voltage reference circuit is disclosed having a common gate differential stage which utilizes the base-to-emitter voltage V.sub.BE, of a bipolar transistor to provide a reference current through a first resistor. Current mirror means are coupled to the differential stage to couple the reference current to second and third resistors which develop the output reference voltage. By ratioing the second and third resistors to the first resistor, a stable output reference voltage which is proportional to the V.sub.BE of the bipolar transistor is provided.

Abstract: A circuit arrangement for deriving a control signal from an audio input signal for level-controlled audio systems comprises a first amplifier/comparator and a first silicon diode for coupling its output signal to a first circuit junction. A feedback circuit is provided for coupling the signal at the first circuit junction to the input of the first amplifier/comparator. A second amplifier/comparator is provided having its output coupled to a second silicon diode which passes its output signal to a second circuit junction. A first feedback resistor is provided to apply the signal at the second circuit junction to the input of the second amplifier/comparator and a second feedback resistor applies an output signal from the second amplifier/comparator to the input thereof.