Abstract: A system, method and processor that mitigates security vulnerabilities using context-dependent address space hiding. In some embodiments, a hardware mechanism allows a more-privileged software component managing multiple less-privileged software components to blind itself against “out-of-context” less-privileged software components. The hardware mechanism can allow the more-privileged software component to dynamically hide a portion of the more-privileged address space related to the “out-of-context” less-privileged software components, based on knowledge of the “in-context” less-privileged software component. A context register is set with a value from which an address range, within the address space of the more-privileged software component, can be determined, where the address range is associated with a first less-privileged software component can be determined.

Abstract: Provided are a computer program product, integrated cache manager, and method for maintaining data in a first level memory and buckets representing regions of memory devices to extend data cache. A plurality of buckets represent distinct regions of memory devices. The buckets are associated with different threshold access count ranges. Data having an access count is stored in one of the buckets associated with a threshold access count range including the access count of the data to store. Data evicted from a first level memory is copied to an initial bucket comprising one of the buckets. Data is moved from a source bucket comprising one of the buckets, including the initial bucket, to a target bucket of the buckets having a target threshold access count range including an access count of the data to move.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: A system, method, and storage medium are provided. The system includes a real-time domain including a real-time cache and a non-real-time domain including a non-real-time cache. The system is configured to implement a cache coherency protocol by indicating that a cache line may be shared between the real-time cache and the non-real-time cache.

Abstract: An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

Abstract: Various illustrative aspects are directed to a data storage device, comprising: one or more disks; a write mechanism configured to write data to disk surfaces of the one or more disks; and one or more processing devices, which are configured to: encode, based on a distributed sector encoding scheme, data into a plurality of logic blocks of data, wherein the logic blocks of data comprise the data to be written being interleaved across a plurality of sectors; assign at least some of the logic blocks to a plurality of containers of two or more container sizes, the container sizes comprising a relatively larger container size and a relatively smaller container size; and output a write signal to the write mechanism to write the logic blocks in accordance with the assigning of the at least some of the logic blocks to the plurality of containers.

Abstract: Systems and methods for cognitive encryption of data are disclosed. The methods may include maintaining a plurality of data storage systems in communication with an external metadata management system, operating the metadata management system to store metadata corresponding to data residing on the plurality of data storage systems, identifying a candidate data set residing on at least one of the plurality of data storage systems on which at least one security action should be performed using information included in the metadata management system, and in response to identifying the candidate data set, identifying the at least one security action.

Abstract: A storage device is provided. A storage device includes a non-volatile memory including a plurality of memory segments, and a storage controller connected to the non-volatile memory through a plurality of channels, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment, wherein the storage controller is configured to generate parity according to speed information received from a host with respect to data to be written to the non-volatile memory and store the parity in at least one of the memory segments.

Abstract: Methods, apparatus, and processor-readable storage media for determining storage system configuration recommendations based on vertical sectors and size parameters using machine learning techniques are provided herein.

Abstract: A system and method for using free space for recovering erasure coding data sets. The method includes segmenting at least one erasure coding data set into at least one stripe based on an erasure coding scheme, wherein each erasure coding data set includes chunks, wherein the chunks include chunks of systematic data and chunks of parity data; distributing the at least one stripe across non-volatile memory nodes based on the erasure coding scheme, wherein each non-volatile memory node is a unit of a non-volatile storage device; and upon a first failure of one of the non-volatile memory nodes: detecting that at least one of the non-volatile memory nodes that is not failed includes a first free space that does not currently store user data; and performing a first recovery process for recovering a first portion of the at least one erasure coding data set, based on the first free space.

Abstract: A processor may allocate a first buffer segment from a buffer pool. The first buffer segment may be configured with a first contiguous range of memory for a first data partition of a data table. The first data partition comprising a first plurality of data blocks. A processor may store the first plurality of data blocks in order into the first buffer segment. A processor may retrieve the target data block from the first buffer segment in response to a data access request for a target data block of the first plurality of data blocks.

Abstract: A method includes defining a plurality of data storage policies, each of the plurality of data storage policies providing rules for storing data among a plurality of data storage locations, each of the plurality of data storage locations having a data storage cost and a data retrieval cost associated therewith; determining a baseline policy distribution among the plurality of data storage policies for an entity; receiving new data items corresponding to the entity; storing the new data items in the plurality of data storage locations using the plurality of data storage policies based on the baseline policy distribution; and determining, using the artificial intelligence engine, a selected one of the plurality of data storage policies to use in storing the new data items corresponding to the entity based on the data storage cost for each of the plurality of data storage locations, and the data retrieval cost for each of the plurality of storage locations.

Abstract: A method is used in managing storage operations in storage systems. Based on a set of criteria, an amount of storage resources required to perform a storage operation is determined. The storage operation is directed to fault tolerant storage devices. The amount of storage resources is allocated prior to start performing the storage operation. The storage operation is performed by using the allocated storage resources.

Abstract: A hard disk drive having a single drive arm with multiple read-write heads for synchronous access to data, wherein the multiple read-write heads are used for synchronous access to shorten the access time of the hard disk drive and the data.

Abstract: A memory management unit includes a controller performing a process translating a requested virtual address to a physical address based on a first region storing first entries indicating the physical address matching a given bit range of the virtual address and a second region storing a second entry associating the bit range with the first entries. When a second entry matching the bit range of a first address is hit in the second region, the controller sets, in the hit second entry, an identification number of a first entry specified by the first address. When the same second entry regarding the first address and a second address is hit and when an identification number specified by the second address is larger than an identification number set in the second entry, the controller obtains, from a memory, information of first entries subsequent to first entries associated with the hit second entry.

Abstract: A secure processing system includes a memory having a secure partition and a non-secure partition, a neural network processing unit (NPU) configured to initiate transactions with the memory, and a memory protection unit (MPU) configured to filter the transactions. Each of the transactions includes at least an address of the memory to be accessed, one of a plurality of first master identifiers (IDs) associated with the NPU, and security information indicating whether the NPU is in a secure state or a non-secure state when the transaction is initiated. The MPU is to selectively deny access to the secure partition of the memory based at least in part on the memory address, the first master ID, and the security information associated with each of the transactions.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, controller, memory, wireless communication function section, and extension register. The controller controls the nonvolatile semiconductor memory device. The memory is serving as a work area of the controller. The wireless communication module has a wireless communication function. The extension register is provided in the memory. The controller processes a first command to read data from the extension register, and a second command to write data to the extension register. The extension register records, an information specifying the type of the wireless communication function in a specific page, and an address information indicating a region on the extension register to which the wireless communication function is assigned.

Abstract: A quantum cache includes a quantum store having an input that receives a quantum state having fundamental quantum properties comprising coherence and is configured to store the quantum state and to preserve a coherence property of stored quantum states to a fidelity level. A fidelity system is coupled to the quantum store and configured to identify if the quantum state that has a coherence property that is not at the fidelity level using monitoring that preserves a coherence property of quantum states to the fidelity level. The fidelity system is further configure to generate classical data about the quantum state if the coherence property is not at the fidelity level, wherein the generated classical data comprises an index associated with the quantum state. Classical data is generated about the quantum state and is transmitted over a classical channel, thereby informing an application that the quantum state having the associated index has the coherence property that is not at the fidelity level.

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.