Patents Examined by Baboucarr Faal
  • Patent number: 11899941
    Abstract: A storage device is provided. A storage device includes a non-volatile memory including a plurality of memory segments, and a storage controller connected to the non-volatile memory through a plurality of channels, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment, wherein the storage controller is configured to generate parity according to speed information received from a host with respect to data to be written to the non-volatile memory and store the parity in at least one of the memory segments.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 13, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Soo-Young Ji
  • Patent number: 11886720
    Abstract: Methods, apparatus, and processor-readable storage media for determining storage system configuration recommendations based on vertical sectors and size parameters using machine learning techniques are provided herein.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 30, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Shou-Huey Jiang, Bina K. Thakkar, Deepak Gowda
  • Patent number: 11886705
    Abstract: A system and method for using free space for recovering erasure coding data sets. The method includes segmenting at least one erasure coding data set into at least one stripe based on an erasure coding scheme, wherein each erasure coding data set includes chunks, wherein the chunks include chunks of systematic data and chunks of parity data; distributing the at least one stripe across non-volatile memory nodes based on the erasure coding scheme, wherein each non-volatile memory node is a unit of a non-volatile storage device; and upon a first failure of one of the non-volatile memory nodes: detecting that at least one of the non-volatile memory nodes that is not failed includes a first free space that does not currently store user data; and performing a first recovery process for recovering a first portion of the at least one erasure coding data set, based on the first free space.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 30, 2024
    Assignee: VAST DATA LTD.
    Inventor: Yogev Vaknin
  • Patent number: 11874765
    Abstract: A processor may allocate a first buffer segment from a buffer pool. The first buffer segment may be configured with a first contiguous range of memory for a first data partition of a data table. The first data partition comprising a first plurality of data blocks. A processor may store the first plurality of data blocks in order into the first buffer segment. A processor may retrieve the target data block from the first buffer segment in response to a data access request for a target data block of the first plurality of data blocks.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Xiaobo Wang, Sheng Yan Sun, Hong Mei Zhang
  • Patent number: 11868613
    Abstract: A method includes defining a plurality of data storage policies, each of the plurality of data storage policies providing rules for storing data among a plurality of data storage locations, each of the plurality of data storage locations having a data storage cost and a data retrieval cost associated therewith; determining a baseline policy distribution among the plurality of data storage policies for an entity; receiving new data items corresponding to the entity; storing the new data items in the plurality of data storage locations using the plurality of data storage policies based on the baseline policy distribution; and determining, using the artificial intelligence engine, a selected one of the plurality of data storage policies to use in storing the new data items corresponding to the entity based on the data storage cost for each of the plurality of data storage locations, and the data retrieval cost for each of the plurality of storage locations.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGE HEALTHCARE HOLDINGS LLC
    Inventors: Philippe Raffy, Jean-Francois Pambrun, David Dubois, Ashish Kumar
  • Patent number: 11868612
    Abstract: A method is used in managing storage operations in storage systems. Based on a set of criteria, an amount of storage resources required to perform a storage operation is determined. The storage operation is directed to fault tolerant storage devices. The amount of storage resources is allocated prior to start performing the storage operation. The storage operation is performed by using the allocated storage resources.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 9, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Robert P. Foley, Peter Puhov
  • Patent number: 11861173
    Abstract: A hard disk drive having a single drive arm with multiple read-write heads for synchronous access to data, wherein the multiple read-write heads are used for synchronous access to shorten the access time of the hard disk drive and the data.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: January 2, 2024
    Assignee: Felicity Taiwan Corporation
    Inventors: Wen-Lang Yu, Chia-Chien Yu
  • Patent number: 11853597
    Abstract: A memory management unit includes a controller performing a process translating a requested virtual address to a physical address based on a first region storing first entries indicating the physical address matching a given bit range of the virtual address and a second region storing a second entry associating the bit range with the first entries. When a second entry matching the bit range of a first address is hit in the second region, the controller sets, in the hit second entry, an identification number of a first entry specified by the first address. When the same second entry regarding the first address and a second address is hit and when an identification number specified by the second address is larger than an identification number set in the second entry, the controller obtains, from a memory, information of first entries subsequent to first entries associated with the hit second entry.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: December 26, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Shinya Hiramoto
  • Patent number: 11847069
    Abstract: A secure processing system includes a memory having a secure partition and a non-secure partition, a neural network processing unit (NPU) configured to initiate transactions with the memory, and a memory protection unit (MPU) configured to filter the transactions. Each of the transactions includes at least an address of the memory to be accessed, one of a plurality of first master identifiers (IDs) associated with the NPU, and security information indicating whether the NPU is in a secure state or a non-secure state when the transaction is initiated. The MPU is to selectively deny access to the secure partition of the memory based at least in part on the memory address, the first master ID, and the security information associated with each of the transactions.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: December 19, 2023
    Assignee: Synaptics Incorporated
    Inventors: Pontus Evert Lidman, Xiao William Cheng, Hongjie Guan, Jingliang Li
  • Patent number: 11836075
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, controller, memory, wireless communication function section, and extension register. The controller controls the nonvolatile semiconductor memory device. The memory is serving as a work area of the controller. The wireless communication module has a wireless communication function. The extension register is provided in the memory. The controller processes a first command to read data from the extension register, and a second command to write data to the extension register. The extension register records, an information specifying the type of the wireless communication function in a specific page, and an address information indicating a region on the extension register to which the wireless communication function is assigned.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: December 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Takashi Wakutsu, Shuichi Sakurai, Kuniaki Ito, Yasufumi Tsumagari
  • Patent number: 11829847
    Abstract: A quantum cache includes a quantum store having an input that receives a quantum state having fundamental quantum properties comprising coherence and is configured to store the quantum state and to preserve a coherence property of stored quantum states to a fidelity level. A fidelity system is coupled to the quantum store and configured to identify if the quantum state that has a coherence property that is not at the fidelity level using monitoring that preserves a coherence property of quantum states to the fidelity level. The fidelity system is further configure to generate classical data about the quantum state if the coherence property is not at the fidelity level, wherein the generated classical data comprises an index associated with the quantum state. Classical data is generated about the quantum state and is transmitted over a classical channel, thereby informing an application that the quantum state having the associated index has the coherence property that is not at the fidelity level.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: November 28, 2023
    Assignee: Qubit Moving and Storage, LLC
    Inventors: Gary Vacon, Kristin A. Rauschenbach
  • Patent number: 11823757
    Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: November 21, 2023
    Assignee: Rambus Inc.
    Inventors: Craig Hampel, Mark Horowitz
  • Patent number: 11797192
    Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with data transmission are described. Data transmission management can include receiving, from an edge device via a radio at a first device, instructions associated with data transmission between a second device in communication with the first device and a cloud service in communication with the first device. Data transmission management can also include managing, at the first device and based on the instructions from the edge device, data received from a memory resource of the second device for transmission to the cloud service and data received from the cloud service for transmission to the memory resource of the second device. Data transmission management can further include enabling transmission of some, none, or all of the data between the cloud service and the memory resource of the second device and vice versa based on the management of the data.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Carly M. Wantulok, Sumana Adusumilli, Chiara Cerafogli
  • Patent number: 11797879
    Abstract: Computer-implemented systems and computer-implemented methods include the following. A request to train a machine-learning (ML) model is received at a training broker. Anonymized data for training the model is obtained by the training broker from each individual data source of a plurality of data sources. The anonymized data is accessed through a data science schema being provided by anonymization of sensitive information of production data from each individual data source. Access to the anonymized data is provided to a data vendor for training the ML model using the anonymized data.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 24, 2023
    Assignee: SAP SE
    Inventors: Peter Eberlein, Volker Driesen
  • Patent number: 11789614
    Abstract: A computer having a plurality of accounts and a storage device having a host interface, a controller, non-volatile storage media, and firmware. An account is configured with at least a predetermined speed in accessing the non-volatile storage media by allocating a number of input/output submission queues in the buffer area of the host. The number can be determined from a ratio between the predetermined speed configured for the account and a saturated speed of the storage device with sufficient submission queues. Data access requests from the account are evenly distributed to the submission queues allocated for the exclusive use by the account; and the controller, configured via the firmware, processes with equal priority the submission queues configured for the storage device. Thus, the account can have at least the predetermined speed in accessing the non-volatile storage media, regardless of how other accounts access the storage device.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 11782846
    Abstract: A digital signal processor, a digital signal processing (DSP) system, and a method for accessing external memory space are disclosed. The digital signal processor may include: a digital signal processing (DSP) core; and a program port and a data port which are connected to the DSP core and configured to access an external memory, where the program port and the data port are respectively configured to communicate with a memory management unit configured for management of an access address.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: October 10, 2023
    Assignee: ZTE CORPORATION
    Inventor: Xueting Sun
  • Patent number: 11782727
    Abstract: Methods, systems, and devices for read prediction during a system boot procedure are described. A memory device may identify a command for a boot procedure and transfer data stored in a memory array to a cache of the memory device. In some cases, the memory device may prefetch data used during the boot procedure and thereby improve the latency of the boot procedure. When the memory device receives a command that requests data stored in the memory array as part of the boot procedure, the memory device may identify a cache hit based on prefetching the requested data before the command is received. In such cases, the memory device may retrieve the prefetched data from the cache.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Nadav Grosz, Jonathan S. Parry
  • Patent number: 11775196
    Abstract: Methods, apparatus, and processor-readable storage media for generating data replication configurations using AI techniques are provided herein. An example computer-implemented method includes obtaining input data pertaining to at least one data replication operation; determining a set of configuration parameters for the at least one data replication operation by applying one or more AI techniques to at least a portion of the input data; and performing one or more automated actions based at least in part on the determined set of configuration parameters for the at least one data replication operation.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: October 3, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Kasnadi Sitaram Nandan, Mohit Kolluri, Vinod Kumar, Sujay Prasheel Sundaram, Sarat Manchiraju, Bijan Kumar Mohanty, Hung T. Dinh, Subrato Nath, Naveen Silvester
  • Patent number: 11775438
    Abstract: System identifies multiple data blocks in workload stored in slow access persistent storage, data blocks copied to fast access persistent storage, and, after speed of accessing workload satisfies threshold, copied data blocks that remained in fast access persistent storage. System annotates some remaining data blocks with cache label and derives features for some data blocks in workload, based on corresponding bits set and/or time stamp. System uses cache labels and features for some data blocks in workload to train machine-learning model to predict which data blocks in workload will remain in fast access persistent storage after workload access satisfies threshold. System derives features for data block requested from production workload.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 3, 2023
    Inventors: Shuai Hua, Yong Zou, Wenhao Hu, Rahul Ugale
  • Patent number: 11775434
    Abstract: The disclosed computer-implemented method may include receiving, from a host via a cache-coherent interconnect, a request to access an address of a coherent memory space of the host. When the request is to write data, the computer-implemented method may include (1) performing, after receiving the data, a post-processing operation on the data to generate post-processed data and (2) writing the post-processed data to a physical address of a device-attached physical memory mapped to the address. When the request is to read data, the computer-implemented method may include (1) reading the data from the physical address of a device-attached physical memory mapped to the address, (2) performing, before responding to the request, a pre-processing operation on the data to generate pre-processed data, and (3) returning the pre-processed data to the external host via the cache-coherent interconnect. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: October 3, 2023
    Assignee: Meta Platforms, Inc.
    Inventors: Narsing Krishna Vijayrao, Christian Markus Petersen