Patents Examined by Baboucarr Faal
  • Patent number: 10180792
    Abstract: Data storage devices may store selected data received from a data source to a buffer memory. The selected data may be copied from the buffer to a non-volatile memory configured for sequential storage. The selected data may then be copied from the buffer to a solid state memory, such as dynamic random access memory. The selected data may be copied from the solid state memory to a main store, such as a magnetic disc memory. If the selected data cannot be found in the solid state memory, the selected data in the non-volatile memory can be copied to the main store.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 15, 2019
    Assignee: Seagate Technology LLC
    Inventors: Mark Gaertner, James D Sawin
  • Patent number: 10162526
    Abstract: Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate an entry associated with the information. The information is associated with a logical address recognized by a host. The entry includes an indicator indicating that the information is to be preserved for a creation of an image of information associated with logical addresses in a logical address space recognized by the host.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Cory J Reche, Phil W. Lee
  • Patent number: 10157130
    Abstract: Systems, methods and a computer program product the differential storage and eviction for information resources from a browser cache. In an embodiment, the present invention provides differential storage and eviction for information resources by storing fetched resources in a memory and assigning, with a processor, a persistence score to the resources. Further embodiments relocate the resources from a sub-cache to a different sub-cache based on their persistence score, and remove the resource from the memory based on the persistence score.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: December 18, 2018
    Assignee: Google LLC
    Inventors: Jim Roskind, Jose Ricardo Vargas Puentes, Ashit Kumar Jain, Evan Martin
  • Patent number: 10152340
    Abstract: In a computer-implemented method for configuring flash cache for input/output operations to a storage device by a plurality of virtual machines an input/output trace log for each of a plurality of virtual machines is accessed. Performance of each of the plurality of virtual machines based on a plurality of configurations of the flash cache is simulated in real-time. A recommendation of the plurality of configurations of the flash cache for the each of the plurality of virtual machines utilizing results from the simulation is generated.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 11, 2018
    Assignee: VMware, Inc.
    Inventors: Sankaran Sivathanu, Niti Khadapkar, Yifan Wang, Tariq Magdon-Ismail, Dilip Patharachalam
  • Patent number: 10126977
    Abstract: Disclosed methods and systems leverage resources in a storage management system to partially synchronize primary data files based on synchronizing selected portions thereof without regard to changes that may be occurring in other non-synchronized portions. Accordingly, a number of primary data files may be partially synchronized by synchronizing designated portions thereof via auto-restore operations from backup data. This approach relies on storage management resources to designate portions of source data that is to be kept synchronized across any number of targets; detect changes to the designated portions; back up changes to secondary storage; and distribute the changes from secondary storage to the associated targets, with minimal impact to the primary data environment. The approach may be mutually applied, so that changes in any one of an associated group of source data files may be likewise detected, backed up, and distributed to the other members of the group.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 13, 2018
    Assignee: Commvault Systems, Inc.
    Inventor: Prosenjit Sinha
  • Patent number: 10127152
    Abstract: Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node. Management of a first group of tracks in the storage managed by the first node is transferred to the second node managing access to a second group of tracks in the storage. After the transferring the management of the tracks, the second node manages access to the first and second groups of tracks and caches accessed tracks from the first and second groups in the second cache of the second node. The second cache of the second node is populated with the tracks in a first cache of the first node.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos, Brian A. Rinaldi
  • Patent number: 10121528
    Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: George Vergis, Kuljit S. Bains, James A. McCall, Ge Chang
  • Patent number: 10101918
    Abstract: Systems and methods for generating hint information associated with a host command are disclosed. In one implementation, a processor of a host system determines whether the host system has initiated a procedure that will send a command to a non-volatile memory system. The processor analyzes at least one of metadata or payload data associated with the command to determine whether the processor is able to generate hint information associated with the at least one of metadata or payload data. The processor generates hint information based on the analysis of the at least one of metadata or payload data, sends the hint information to the non-volatile memory system, and sends the command to the non-volatile memory system.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 16, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Judah Gamliel Hahn, Joseph R. Meza, William L. Guthrie
  • Patent number: 10095435
    Abstract: In one embodiment, a method of operating memory circuitry that is coupled to processing circuitry and memory controller circuitry may include a step to initialize a first portion of the memory circuitry with the memory controller circuitry. The method may also include a step to store startup sequence information onto the first portion of the memory circuitry while the memory controller circuitry initializes a second portion of the memory circuitry with the processing circuitry. The second portion of memory circuitry may be different from the first portion of the memory circuitry.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 9, 2018
    Assignee: Altera Corporation
    Inventor: Chin Liang See
  • Patent number: 10095442
    Abstract: A memory device includes a memory unit, a communication interface through which commands are received from a plurality of hosts, and a controller configured to store the commands in a queue and determine an order of execution of the commands according to when the commands were added to the queue and whether or not the commands issued from a host that is designated as a priority host. The controller determines the commands issued from the priority host to be executed prior to other commands that were not issued from the priority host, and determines the other commands to be executed in the order they were added to the queue.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 9, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Nobuyuki Myouga
  • Patent number: 10073773
    Abstract: Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped to storage. Data stored in circular buffers is paged in and out to a second level memory. State information for each logical element is also saved and restored using paging memory. Logical elements such as processing elements are provided instructions via circular buffers. The instructions enable a group of processing elements to perform operations implementing a desired functionality. That functionality is changed by updating the circular buffers with new instructions that are transferred from paging memory. The previous instructions can be saved off in paging memory before the new instructions are copied over to the circular buffers. This enables the hardware to be rapidly reconfigured amongst multiple functions.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 11, 2018
    Assignee: Wave Computing, Inc.
    Inventor: Christopher John Nicol
  • Patent number: 10067880
    Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Edwards, Robert Galbraith, Adrian C. Gerhard, Daniel F. Moertl, Gowrisankar Radhakrishnan, Rick A. Weckwerth
  • Patent number: 10055167
    Abstract: Correlating two storage rings based on an access rate for an object. A correlative dual hash ring includes a first ring of storage drives and a second ring of storage drives. Objects and replicas are allocated to either a first ring or a second ring.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jiming Dai, Xiao Lei Hu, Mengze Liao, Yangming Wang, Xiao Hua Zeng
  • Patent number: 10042757
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, controller, memory, wireless communication function section, and extension register. The controller controls the nonvolatile semiconductor memory device. The memory is serving as a work area of the controller. The wireless communication module has a wireless communication function. The extension register is provided in the memory. The controller processes a first command to read data from the extension register, and a second command to write data to the extension register. The extension register records, an information specifying the type of the wireless communication function in a specific page, and an address information indicating a region on the extension register to which the wireless communication function is assigned.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 7, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Wakutsu, Shuichi Sakurai, Kuniaki Ito, Yasufumi Tsumagari
  • Patent number: 10031849
    Abstract: Data can be stored in a multi-level cache hierarchy memory system by, for example, storing valid data associated with a cacheline in a primary location in a first cache memory location. The first cache memory also stores location information about an alternative location in a second cache memory associated with the cacheline. Space is allocated in the alternative location of the second cache memory to store data associated with the cacheline.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: July 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer
  • Patent number: 10025715
    Abstract: Determining, by a processor having a cache, if data in the cache is to be monitored for cache coherency conflicts in a transactional memory (TM) environment. A processor executes a TM transaction, that includes the following. Executing a memory data access instruction that accesses an operand at an operand memory address. Based on either a prefix instruction associated with the memory data access instruction, or an operand tag associated with the operand of the memory data access instruction, determining whether a cache entry having the operand is to be marked for monitoring for cache coherency conflicts while the processor is executing the transaction. Based on determining that the cache entry is to be marked for monitoring for cache coherency conflicts while the processor is executing the transaction, marking the cache entry for monitoring for conflicts.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 10019368
    Abstract: A placement policy enables the selective storage of cachelines in a multi-level cache hierarchy: Reuse behavior of a cacheline is tracked during execution of an application in both a first level cache memory and a second level cache memory. A cache placement policy for the cacheline is determined based on the tracked reuse behavior.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: July 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer
  • Patent number: 10013235
    Abstract: Systems and methods of queuing data for multiple readers and writers are provided. Enqueuing operations are disclosed that can process write functionality and can determine whether ring buffers have potentially filled, and dynamically declare a new ring buffer at a multiple of capacity of the current ring. Dequeuing operations are disclosed that can process read functionality for advancing control and determining whether and when to free ring buffers from memory.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: July 3, 2018
    Assignee: TRAVELPORT, LP
    Inventor: Bryan Karr
  • Patent number: 10013182
    Abstract: A system and method for data storage management is disclosed. The method includes determining, by an access tracking component, a quantity of access requests for at least one data block, and determining a quantity of current copies of the data block. The method also includes creating, by a duplication component, at least one additional copy of the data block when the quantity of the access requests exceeds an access request threshold. Additionally, a deduplication component removes at least one current copy of the data block when the quantity of the access requests falls below the access request threshold. The access request threshold can be a threshold number of access requests for the data block, the presence of an input/output bottleneck, or a given length of a read latency when accessing the data block. Further, data coloring techniques can be used to distribute current copies of the data block.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joseph W. Dain, Itzhack Goldberg, Gregory T. Kishi, Daniel I. Tan
  • Patent number: 10007433
    Abstract: Systems and methods for performing adaptive host memory buffer caching of transition layer tables (FTL tables) are disclosed. In one form a non-volatile memory system receives, in conjunction with receiving a first host command from a host system, hint information from the host system identifying a file stored at the non-volatile memory system that the host system will read data from. The non-volatile memory system identifies one or more FTL tables that are associated with data of the file identified in the hint information and sends the one or more FTL tables to the host system for storage in a host memory buffer at the host system. After sending the one or more FTL tables to the host system, the non-volatile memory system receives a second host command from the host system, the host command including an instruction to read data from one or more physical block addresses at the non-volatile memory system storing data of the file.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: June 26, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Judah Gamliel Hahn