Abstract: Computer-implemented systems and computer-implemented methods include the following. A request to train a machine-learning (ML) model is received at a training broker. Anonymized data for training the model is obtained by the training broker from each individual data source of a plurality of data sources. The anonymized data is accessed through a data science schema being provided by anonymization of sensitive information of production data from each individual data source. Access to the anonymized data is provided to a data vendor for training the ML model using the anonymized data.

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with data transmission are described. Data transmission management can include receiving, from an edge device via a radio at a first device, instructions associated with data transmission between a second device in communication with the first device and a cloud service in communication with the first device. Data transmission management can also include managing, at the first device and based on the instructions from the edge device, data received from a memory resource of the second device for transmission to the cloud service and data received from the cloud service for transmission to the memory resource of the second device. Data transmission management can further include enabling transmission of some, none, or all of the data between the cloud service and the memory resource of the second device and vice versa based on the management of the data.

Abstract: A computer having a plurality of accounts and a storage device having a host interface, a controller, non-volatile storage media, and firmware. An account is configured with at least a predetermined speed in accessing the non-volatile storage media by allocating a number of input/output submission queues in the buffer area of the host. The number can be determined from a ratio between the predetermined speed configured for the account and a saturated speed of the storage device with sufficient submission queues. Data access requests from the account are evenly distributed to the submission queues allocated for the exclusive use by the account; and the controller, configured via the firmware, processes with equal priority the submission queues configured for the storage device. Thus, the account can have at least the predetermined speed in accessing the non-volatile storage media, regardless of how other accounts access the storage device.

Abstract: Methods, systems, and devices for read prediction during a system boot procedure are described. A memory device may identify a command for a boot procedure and transfer data stored in a memory array to a cache of the memory device. In some cases, the memory device may prefetch data used during the boot procedure and thereby improve the latency of the boot procedure. When the memory device receives a command that requests data stored in the memory array as part of the boot procedure, the memory device may identify a cache hit based on prefetching the requested data before the command is received. In such cases, the memory device may retrieve the prefetched data from the cache.

Abstract: A digital signal processor, a digital signal processing (DSP) system, and a method for accessing external memory space are disclosed. The digital signal processor may include: a digital signal processing (DSP) core; and a program port and a data port which are connected to the DSP core and configured to access an external memory, where the program port and the data port are respectively configured to communicate with a memory management unit configured for management of an access address.

Abstract: Methods, apparatus, and processor-readable storage media for generating data replication configurations using AI techniques are provided herein. An example computer-implemented method includes obtaining input data pertaining to at least one data replication operation; determining a set of configuration parameters for the at least one data replication operation by applying one or more AI techniques to at least a portion of the input data; and performing one or more automated actions based at least in part on the determined set of configuration parameters for the at least one data replication operation.

Abstract: System identifies multiple data blocks in workload stored in slow access persistent storage, data blocks copied to fast access persistent storage, and, after speed of accessing workload satisfies threshold, copied data blocks that remained in fast access persistent storage. System annotates some remaining data blocks with cache label and derives features for some data blocks in workload, based on corresponding bits set and/or time stamp. System uses cache labels and features for some data blocks in workload to train machine-learning model to predict which data blocks in workload will remain in fast access persistent storage after workload access satisfies threshold. System derives features for data block requested from production workload.

Abstract: The disclosed computer-implemented method may include receiving, from a host via a cache-coherent interconnect, a request to access an address of a coherent memory space of the host. When the request is to write data, the computer-implemented method may include (1) performing, after receiving the data, a post-processing operation on the data to generate post-processed data and (2) writing the post-processed data to a physical address of a device-attached physical memory mapped to the address. When the request is to read data, the computer-implemented method may include (1) reading the data from the physical address of a device-attached physical memory mapped to the address, (2) performing, before responding to the request, a pre-processing operation on the data to generate pre-processed data, and (3) returning the pre-processed data to the external host via the cache-coherent interconnect. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

Abstract: Apparatuses and methods related to implementing refresh and access modes for memory. The refresh and access modes can be used to configure a portion of memory. The portions of memory can correspond to protected regions of memory. The refresh and access modes can influence the security level of data stored in the protected regions of memory.

Abstract: Methods, apparatus, and processor-readable storage media for automated storage capacity provisioning using machine learning techniques are provided herein. An example computer-implemented method includes obtaining a user-provided input comprising an identification of an amount of storage capacity to be provisioned from a storage system; determining an amount of time for which the amount of storage capacity to be provisioned will last in connection with the storage system by processing the user-provided input in connection with historical data pertaining to storage utilization using one or more machine learning techniques; outputting, to the user, the determined amount of time for which the amount of storage capacity to be provisioned will last; and performing one or more automated actions based at least in part on feedback from the user in response to the outputting of the determined amount of time for which the amount of storage capacity to be provisioned will last.

Abstract: The technology disclosed herein pertains to a system and method for storing data on a storage media using both down-track super parity and cross-track super parity. Specifically, a method disclosed herein provides for generating down-track super parity values for data on the plurality of tracks and storing the down-track super parity values on a down-track super parity row of the storage block and generating cross-track super parity values for data on the plurality of rows and storing the cross-track super parity values on a cross-track upper parity track, wherein the cross-track super parity value for any given row is generated by inputting the data on the given row into an exclusive-OR (XOR) gate.

Abstract: A garbage collection technology for a storage medium that includes a plurality of blocks, where each storage unit has a collection parameter related to data in one of the blocks, and where each block includes a plurality of pages. A group of blocks is selected from the plurality of blocks based on the collection parameter. A difference between values of collection parameters of any two blocks in the group of blocks is not greater than a preset value. Data in a first valid page and a second valid page in the group of blocks is replicated to a same destination block, to facilitate garbage collection.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may receive a prefetch request to retrieve data for a host having a promoted stream. The controller may access a frozen time table indicating hosts for which data has been prefetched and frozen times associated with the host and other hosts. The controller can determine whether the host has a higher priority over other hosts included in the frozen time table based on corresponding frozen times and data access parameters associated with the host. The controller may determine to prefetch the data for the host in response to the prefetch request when the host has a higher priority than the other hosts. The controller can receive a host read command associated with the promoted stream from the host and provide the prefetched data to the host in response to the host read command.

Abstract: A processing unit includes a processor core and an associated cache memory. The cache memory establishes a reservation of a hardware thread of the processor core for a store target address and services a store-conditional request of the processor core by conditionally updating the shared memory with store data based on the whether the hardware thread has a reservation for the store target address. The cache memory receives a hint associated with the store-conditional request indicating an intent of the store-conditional request. The cache memory protects the store target address against access by any conflicting memory access request during a protection window extension following servicing of the store-conditional request. The cache memory establishes a first duration for the protection window extension based on the hint having a first value and establishes a different second duration for the protection window extension based on the hint having a different second value.

Abstract: A memory system includes at least one memory device and a controller coupled with the at least one memory device via plural communication lines. The at least one memory device includes plural units, each unit including plural memory cells, each memory cell capable of storing multi-bit data. The controller determines a hierarchy used for determining an access sequence access to the plural communication lines, the plural units, and plural bits of the multi-bit data, and accesses memory cells included in the at least one memory device based on the hierarchy for a read or write operation regarding transmitted data.

Abstract: The disclosed computer-implemented method may include (1) receiving, at a storage device via a cache-coherent interconnect, a first request to access data at one or more host addresses of a coherent memory space of an external host processor, (2) updating, in response to the first request, one or more statistics associated with accessing the data at the one or more host addresses, (3) receiving, at the storage device via the cache-coherent interconnect, a second request to perform an operation associated with the one or more statistics, and (4) using the one or more statistics to perform the operation. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method, computer program product, and computing system for receiving, at a cache memory system, a write request for writing data to a storage system. A data reduction rate may be predicted for the write request. One or more portions of memory within the storage system may be allocated based upon, at least in part, the predicted data reduction rate for the write request. The write request may be flushed from the cache memory system to the allocated one or more portions of memory within the storage system.

Abstract: One example method includes determining a modulus such as a Weibull modulus for a recovery operation. Enablement and disablement of a read ahead cache are performed based on the modulus. The modulus is a linearization of a cumulative distribution function, where failures correspond to non-sequential accesses and successes correspond to sequential accesses.

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.