Patents Examined by Baboucarr Faal
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Patent number: 10782903Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of nonvolatile memory dies, and a controller. The controller classifies the nonvolatile memory dies into a plurality of physical sets such that each of the nonvolatile memory dies belongs to only one physical set. The controller creates a plurality of storage regions which share each of the physical sets and each of which spans the physical sets. The controller sets one of the physical sets to a first mode for permitting a write operation and a read operation, and sets each of the other physical sets to a second mode for permitting a read operation and inhibiting a write operation.Type: GrantFiled: May 20, 2019Date of Patent: September 22, 2020Assignee: Toshiba Memory CorporationInventor: Shinichi Kanno
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Patent number: 10783074Abstract: A controller includes a memory device storing data and including a memory interface a processor; and a memory, wherein, when data is stored in all pages of an open block of a memory device, the processor determines a number of valid pages in the open block and performs a garbage collection on the open block when the number of valid page(s) is determined to be less than or equal to a threshold value, wherein the number ranges from zero to the total number of pages in the open block.Type: GrantFiled: October 24, 2018Date of Patent: September 22, 2020Assignee: SK hynix Inc.Inventor: Hyeong-Ju Na
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Patent number: 10754766Abstract: A method for memory management includes allocating an available block of memory for use by a first object, determining that the block of memory includes at least a portion of a second object, the second object no longer being used by an application associated with the second object, determining that the second object utilized at least one resource that was not shutdown, releasing the at least one resource, and writing to the block of memory with the first object.Type: GrantFiled: March 21, 2014Date of Patent: August 25, 2020Assignee: Red Hat Israel, Ltd.Inventor: Michael Pasternak
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Patent number: 10755794Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.Type: GrantFiled: August 30, 2017Date of Patent: August 25, 2020Assignee: Rambus Inc.Inventors: Craig Hampel, Mark Horowitz
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Patent number: 10754789Abstract: Provided are systems and methods for an address translation circuit for a memory controller. The address translation circuit can include an address translation table. A first set of rows in the address translation table can be associated with all virtual machine identifiers supported by the memory controller. A second set of rows can be associated with only a particular virtual machine identifier. The address translation circuit can receive an input address for a transaction to processor memory. The address translation circuit can determine an index by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes the address translation for the input address. The address translation circuit can generate and output a translated address using the address translation.Type: GrantFiled: November 15, 2017Date of Patent: August 25, 2020Assignee: Amazon Technologies, Inc.Inventors: Thomas A. Volpe, Steven Scott Larson
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Patent number: 10747462Abstract: A data processing system includes a host device including a first volatile memory which includes an exclusive region and a shared region, and a first control unit; and a data storage device including a second control unit, and configured to store data to be accessed by the host device, wherein the first control unit adds a header information including an identification information and a state information, to data to be stored in the data storage device, and stores the data added with the header information, in the shared region, according to a request of the second control unit.Type: GrantFiled: July 14, 2016Date of Patent: August 18, 2020Assignee: SK hynix Inc.Inventor: Soong Sun Shin
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Patent number: 10740233Abstract: According to an example, cache operations may be managed by detecting that a cacheline in a cache is being dirtied, determining a current epoch number, in which the current epoch number is associated with a store operation and wherein the epoch number is incremented each time a thread of execution completes a flush-barrier checkpoint, and inserting an association of the cacheline to the current epoch number into a field of the cacheline that is being dirtied.Type: GrantFiled: October 30, 2015Date of Patent: August 11, 2020Assignee: Hewlett Packard Enterprise Development LPInventor: Derek Alan Sherlock
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Patent number: 10713177Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.Type: GrantFiled: September 9, 2016Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Gilbert Neiger, Baiju V. Patel, Gur Hildesheim, Ron Rais, Andrew V. Anderson, Jason W. Brandt, David M. Durham, Barry E. Huntley, Raanan Sade, Ravi L. Sahita, Vedvyas Shanbhogue, Arumugam Thiyagarajah
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Patent number: 10684959Abstract: A server LPAR operating in a virtualized computer shares pages with client LPARs using a shared memory region (SMR). A virtualization function of the computer receives a get-page-ID request associated with a client LPAR to identify a physical page corresponding to a shared page included in the SMR. The virtualization function requests the server LPAR to provide an identity of the physical page. The virtualization function receives a page-ID response comprising the identity of a server LPAR logical page that corresponds to the physical page. The virtualization element determines a physical page identity and communicates the physical page identity to the client LPAR. The virtualization element receives a page ID enter request and enters an identity of the physical page into a translation element of the computer to associate a client LPAR logical page with the physical page.Type: GrantFiled: January 7, 2019Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Ramanjaneya S. Burugula, Niteesh K. Dubey, Joefon Jann, Pratap C. Pattnaik, Hao Yu
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Patent number: 10678648Abstract: A method, an apparatus, and a system for migrating virtual machine backup information, which implement backup information migration after a virtual machine is migrated. The method includes: receiving, by a first backup server, a migration trigger message, where the migration trigger message carries pre-migration virtual-machine identification information and indication information of a second backup server; determining, by the first backup server, backup information of the virtual machine according to the pre-migration virtual-machine identification information; and sending, by the first backup server, the backup information to the second backup server. Therefore, the migrated virtual machine inherits backup information existing before the migration, such that the migrated virtual machine continues to be protected by backup data existing before the migration, and data of the virtual machine is backed up according to a backup policy existing before the migration.Type: GrantFiled: June 6, 2017Date of Patent: June 9, 2020Assignee: Huawei Technologies Co., Ltd.Inventors: Heng Huang, Lei Zhang, Hua Cheng
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Patent number: 10664300Abstract: A balloon memory fragmentation reduction system includes a memory, at least one processor in communication with the memory, a guest operating system (OS) including a device driver, and a hypervisor executing on the at least one processor. The hypervisor is configured to record an amount of memory allocated by the device driver of the guest OS, locate a contiguous region of guest memory addresses according to the amount of memory allocated by the device driver, reserve the contiguous region of guest memory addresses, and notify the guest OS that the contiguous region of guest memory addresses is reserved.Type: GrantFiled: December 1, 2017Date of Patent: May 26, 2020Assignee: Red Hat, Inc.Inventors: David Hildenbrand, Michael Tsirkin
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Patent number: 10649697Abstract: An information providing system and method, including a computer, for providing time taken to read a file, which includes an acquisition unit. The acquisition unit obtains information on a recording position of a file when the file is recorded in a storage device. A recording unit writes information on the obtained recording position to an index referred to access the file. A calculation unit calculates time taken to read the file using the information on the recording position written to the index in response to a request to obtain the time taken to read the file, and providing the calculated time to a requester that requests the time.Type: GrantFiled: October 20, 2015Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Terue Watanabe, Noriko Yamamoto
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Patent number: 10642978Abstract: Methods of detecting malicious code injected into memory of a computer system are disclosed. The memory injection detection methods may include enumerating memory regions of an address space in memory of computer system to create memory region address information. The memory region address information may be compared to loaded module address information to facilitate detection of malicious code memory injection.Type: GrantFiled: August 4, 2017Date of Patent: May 5, 2020Assignee: Ivanti, Inc.Inventor: Daniel Teal
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Patent number: 10628066Abstract: A storage infrastructure and method for efficiently handing block I/O requests. An infrastructure is described that includes flash memory and a controller that includes: a two dimensional (2D) linked list structure for temporarily storing BIO requests, wherein each BIO request specifies a set of LBAs and wherein the 2D linked list structure includes N vertical linked lists; a BIO request loader that applies a hash function to each LBA in a received BIO request to associate each LBA to one of N hash values, and loads the received BIO request into a horizontal linked list in the 2D linked list structure in which each LBA resides within a vertical linked list based on an associated hash values; and a linked list manager that determines which LBAs in the 2D linked list structure are eligible for processing and when a horizontal linked list can be removed.Type: GrantFiled: May 21, 2018Date of Patent: April 21, 2020Assignee: SCALEFLUX, INCInventors: Qi Wu, Qing Li, Jiangpeng Li
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Patent number: 10620840Abstract: Provided are a computer product, method, and system to generate a virtual subsystem to process read and write requests to storage devices. A virtual subsystem is configured in the memory to provide a representation of a subsystem presented to at least one host system. The at least one host system is to communicate with the virtual subsystem to access the at least one storage device. At least one virtual namespace is configured in the memory for the virtual subsystem. Each of the at least one virtual namespace maps to at least one physical namespace in at least one storage device. Each virtual namespace is assigned to one host system to use to direct read and write requests to the at least one physical namespace of the at least one storage device assigned to the virtual namespace.Type: GrantFiled: May 27, 2016Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: James P. Freyensee, Dave B. Minturn, Phil C. Cayton, Jay E. Sternberg, Anthony J. Knapp
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Patent number: 10621085Abstract: A storage system and a system garbage collection method are provided. The storage system includes a first controller, a second controller, and a solid state disk. The first controller or the second controller manages storage space of the solid state disk in a unit of a segment. The first controller is configured to perform system garbage collection on multiple segments of segments managed by the first controller. The second controller is configured to: when the first controller performs system garbage collection, perform system garbage collection on multiple segments of segments managed by the second controller. The multiple segments of the segments managed by the first controller and the multiple segments of the segments managed by the second controller are allocated within a same time period. Therefore, a quantity of times of write amplification in the solid state disk can be reduced.Type: GrantFiled: August 9, 2018Date of Patent: April 14, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Qiang Xue, Peijun Jiang
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Patent number: 10621101Abstract: An overlay of a file-based write filter can be freed up to thereby minimize the likelihood that the overlay will become full and force a system reboot. An overlay-managing write filter can be employed in conjunction with the file-based write filter to monitor files that are stored in the overlay and move files that are not currently being accessed. If a request is made to access a moved file, the overlay-managing write filter can modify the request so that it targets the location of the moved file rather than the location of the original file on the protected volume. In this way, the fact that modified files are being moved from the overlay but not discarded can be hidden from the file-based write filter. As a result, the effective size of the overlay will be increased while still allowing the file-based write filter to function in a normal fashion.Type: GrantFiled: February 1, 2017Date of Patent: April 14, 2020Assignee: Wyse Technology L.L.C.Inventors: Salil S Joshi, Puneet Kaushik
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Patent number: 10613799Abstract: A computer-implemented method includes identifying a storage migration. The storage migration is associated with a storage area network. The storage migration has a storage migration rate associated therewith. The method includes identifying an input/output throughput. The input/output throughput is associated with the storage area network. The input/output throughput stores a throughput rate for the storage area network. The method includes identifying a service level agreement rate for the input/output throughput. The method includes identifying a non-essential workload. The non-essential workload stores a non-essential workload rate associated therewith. The non-essential workload includes that portion of said input/output throughput that is for one or more background processes. The method includes determining an analyzed rate based on the throughput rate, the service level agreement rate, and the non-essential workload rate.Type: GrantFiled: April 19, 2019Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: John V. Delaney, Anthony M. Hunt, Maeve M. O'Reilly, Daniel P. Toulan, Clea A. Zolotow
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Patent number: 10599461Abstract: This disclosure generally relates to hypervisor memory virtualization. In an example, multiple page table stages may be used to provide a page table that may be used by a processor when processing a workload for a nested virtual machine. An intermediate (e.g., nested) hypervisor may request an additional page table stage from a parent hypervisor, which may be used to virtualize memory for one or more nested virtual machines managed by the intermediate hypervisor. Accordingly, a processor may use the additional page table stages to ultimately translate a virtual memory address for a nested virtual machine to a physical memory address.Type: GrantFiled: January 19, 2018Date of Patent: March 24, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Aditya Bhandari, Bruce J. Sherwin, Jr., Xin David Zhang
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Patent number: 10599367Abstract: A computer-implemented method includes identifying a storage migration. The storage migration is associated with a storage area network. The storage migration has a storage migration rate associated therewith. The method includes identifying an input/output throughput. The input/output throughput is associated with the storage area network. The input/output throughput stores a throughput rate for the storage area network. The method includes identifying a service level agreement rate for the input/output throughput. The method includes identifying a non-essential workload. The non-essential workload stores a non-essential workload rate associated therewith. The non-essential workload includes that portion of said input/output throughput that is for one or more background processes. The method includes determining an analyzed rate based on the throughput rate, the service level agreement rate, and the non-essential workload rate.Type: GrantFiled: June 4, 2019Date of Patent: March 24, 2020Assignee: International Business Machines CorporationInventors: John V. Delaney, Anthony M. Hunt, Maeve M. O'Reilly, Daniel P. Toulan, Clea A. Zolotow