Patents Examined by Baboucarr Faal
  • Patent number: 10599208
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller executes access to the nonvolatile memory based on a command from a host device. The controller includes a processor, a data memory and a monitoring circuit. The monitoring circuit monitors writing to the data memory by a certain processing circuit in the controller and transmits a first notification to the processor when receiving the writing.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: March 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyasu Nakatsuka, Mitsunori Tadokoro, Mitsuru Anazawa
  • Patent number: 10592407
    Abstract: Short pointer mode applications are able to execute in long pointer mode environments. A plurality of actions is performed to prepare a short pointer mode application for execution in the long pointer mode environment. These actions include allocating memory for one or more in-memory short pointers of the application. The memory being allocated for an in-memory short pointer is of a size corresponding to a size of the in-memory short pointer. Further, a register is allocated for an in-register short pointer of the application. The register is allocated at a size corresponding to a long pointer mode. The size corresponding to the long pointer mode is different from the size of the in-memory short pointer.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10585756
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium (which is not a transitory signal per se) having program instructions embodied therewith which are readable and/or executable by a processor to cause the processor to perform a method which includes: receiving data at a secondary storage volume in a secondary system from a primary storage volume in a primary system. Upon receiving a read request at the secondary system, the method includes: reading the requested data from the secondary storage volume; sending a request to the primary system for the requested data after determining that it is not in the secondary storage volume; receiving the data from the primary system; supplying the requested data; storing the data received from the primary system in the secondary storage volume; updating a secondary record; and sending a message to the primary system for updating a primary record.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrea Sipka, John P. Wilkinson
  • Patent number: 10585790
    Abstract: Short pointer mode applications are able to execute in long pointer mode environments. A plurality of actions is performed to prepare a short pointer mode application for execution in the long pointer mode environment. These actions include allocating memory for one or more in-memory short pointers of the application. The memory being allocated for an in-memory short pointer is of a size corresponding to a size of the in-memory short pointer. Further, a register is allocated for an in-register short pointer of the application. The register is allocated at a size corresponding to a long pointer mode. The size corresponding to the long pointer mode is different from the size of the in-memory short pointer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10579276
    Abstract: A storage scheme allocates portions of a logical volume to storage nodes in excess of the capacity of the storage nodes. Slices of the storage nodes and segments of slices are allocated in response to write requests such that actual allocation on the storage nodes is only in response to usage. Segments are identified with virtual segment identifiers that are retained when segments are moved to a different storage node. Logical volumes may therefore be moved seamlessly to different storage nodes to ensure sufficient storage capacity. Data is written to new locations in segments having space and a block map tracks the last segment to which data for a given address is written. Garbage collection is performed to free segments that contain invalid data, i.e. data for addresses that have been subsequently written to.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: March 3, 2020
    Assignee: ROBIN SYSTEMS, INC.
    Inventors: Dhanashankar Venkatesan, Partha Sarathi Seetala
  • Patent number: 10572155
    Abstract: A data storage device includes a nonvolatile memory device; and a controller including a plurality of buffers and suitable for, when a program fail occurs in the nonvolatile memory device, transmitting exchange data stored in an optional exchange buffer among the plurality of buffers, to the nonvolatile memory device, storing and updating, in the exchange buffer, failed program data received from the nonvolatile memory device, and transmitting the updated program data to the nonvolatile memory device.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Beom Rae Jeong
  • Patent number: 10572181
    Abstract: A method for use with a garbage collector to provide different garbage collections is disclosed. The garbage collections are concurrent garbage collection provided in a dedicated thread concurrently running in a computing device with a mutator thread. A heap size stage, from multiple heap size stages including a heap size growth stage and a heap size stable stage, is determined from a free space amount subsequent a garbage collection. A heap stable garbage collection is applied in response to the heap size stage being the heap size stable stage. A heap growth garbage collection is applied in response to the heap size stage being the heap size growth stage.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: February 25, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Maoni Zhang Stephens, Patrick H. Dussud
  • Patent number: 10558578
    Abstract: Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: February 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Oluleye Olorode, Ramakrishnan Venkatasubramanian
  • Patent number: 10558362
    Abstract: Operating a data storage system comprising a plurality of disk drives and a storage controller connected to the disk drives. A first subset and a second subset of the plurality of disk drives are operated as short stroked disk drives and non-short stroked disk drives, respectively. Priority storage spaces are defined including a high priority storage space, a moderate priority storage space, and a low priority storage space. Data is received including associated access rates for each portion of the data. One of the priority storage spaces is identified to store a portion of the data, based on the access rates for each portion of the data. Data accessed most frequently is stored in the high priority storage space, data accessed least frequently is stored in the low priority storage space, and the remaining data is stored in the moderate priority storage space.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: John P. Agombar, Ian Boden, Alastair Cooper, Gordon D. Hutchison
  • Patent number: 10558569
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 11, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Hans Boehm, Dhruva Chakrabarti
  • Patent number: 10552068
    Abstract: Disclosed are a device and method for accessing to a RAM and a control chip. The device includes a register module configured to acquire attribute information and startup information configured by a CPU and send the startup information to a searching and matching module, and also configured to store data information successfully matched by the searching and matching module and instruct the CPU to read the data information. The searching and matching module is configured to send address information to an RAM interface module according to the startup information, and also configured to acquire the data information sent by the RAM interface module, match the data information based on the attribute information in the register module and send the data information to the register module after matching is successful.
    Type: Grant
    Filed: June 12, 2016
    Date of Patent: February 4, 2020
    Assignee: Sanechips Technology Co., Ltd.
    Inventor: Meng Zhang
  • Patent number: 10552324
    Abstract: Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node. Management of a first group of tracks in the storage managed by the first node is transferred to the second node managing access to a second group of tracks in the storage. After the transferring the management of the tracks, the second node manages access to the first and second groups of tracks and caches accessed tracks from the first and second groups in the second cache of the second node. The second cache of the second node is populated with the tracks in a first cache of the first node.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos, Brian A. Rinaldi
  • Patent number: 10540115
    Abstract: Memory systems may include a memory including a plurality of dies, and a controller suitable for receiving a host read request during programming of one of the plurality of dies; determining a suspendable die among the plurality of dies based on a suspension threshold; and suspending the determined suspendable die and performing the received request.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Wei Zang, Chun Hok Ho
  • Patent number: 10534703
    Abstract: A memory system may include a nonvolatile memory device including a plurality of blocks each including a plurality of pages, and a controller that selects a mapping block from the plurality of blocks, stores address information corresponding to each of other blocks, except for the mapping block and a free block among the plurality of blocks, in each of the plurality of pages, searches for a block including no valid page among the other blocks, and invalidates a page of the mapping block storing the address information corresponding to the searched block.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10534715
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more page walk caches, where operation includes: receiving, at a load/store slice, an instruction to be issued; determining, at the load/store slice, a process type indicating a source of the instruction to be a host process or a guest process; and determining, in accordance with an allocation policy and in dependence upon the process type, an allocation of an entry of the page walk cache, wherein the page walk cache comprises one or more entries for both host processes and guest processes.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dwain A. Hicks, Jonathan H. Raymond, George W. Rohrbaugh, III, Shih-Hsiung S. Tung
  • Patent number: 10521353
    Abstract: A data storage device includes a nonvolatile memory device and a controller configured to control an operation of the nonvolatile memory device. The controller includes an RAM in which a category table that categories with respect to LBAs are defined and a read voltage table that read voltages with respect to the categories are set are stored and a controller configured to, when a read request and an LBA to be read are received from a host apparatus, determine a category corresponding to the LBA with reference to the category table and perform a read operation on a read-requested memory cell of the nonvolatile memory device by applying a read voltage corresponding to the determined category to the memory cell with reference to the read voltage table.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Su Jin Lim
  • Patent number: 10521354
    Abstract: Apparatuses, methods and storage medium associated with computing that include usage and backup of persistent memory are disclosed herein. In embodiments, an apparatus for computing may comprise one or more processors and persistent memory to host operation of one or more virtual machines; and one or more page tables to store a plurality of mappings to map a plurality of virtual memory pages of a virtualization of the persistent memory of the one or more virtual machines to a plurality of physical memory pages of the persistent memory allocated to the one or more virtual machines. The apparatus may further include a memory manager to manage accesses of the persistent memory that includes a copy-on-write mechanism to service write instructions that address virtual memory pages mapped to physical memory pages that are marked as read-only. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Kun Tian
  • Patent number: 10503403
    Abstract: A control unit determines a storage location of copy target data managed by a first controller module, based on configuration information. When a first transmission buffer included in the first controller module is the storage location of the copy target data, the control unit stores the copy target data in the first transmission buffer. When a second transmission buffer different from the first transmission buffer is the storage location of the copy target data, the control unit stores the copy target data in the second transmission buffer via a corresponding second controller module.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: December 10, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hidenori Yamada
  • Patent number: 10481803
    Abstract: Technology is provided for updating a data set in a data storage system. In an example data storage system, the system stores a separate copy of an initial data set on each one of a plurality of storage devices, one of which is designated as a leader storage device. The system receives update data and transmits it to each other one of the plurality of replica storage devices. The system updates the copy of the initial data set stored on a replica storage device based on the updated data, resulting in an updated data set and adds a provisional marker to the updated data set. The system transmits an update notification to each of the other replica storage devices. Responsive to determining that update notifications have been received from a threshold number of replica storage, the system removes the provisional marker from the updated data set.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 19, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Arman Fazeli Chaghooshi, Lluis Pamies-Juarez, Cyril Guyot
  • Patent number: 10474832
    Abstract: The present invention relates to a technology that performs: checking an integrity of a paravirtualization agent before executing the paravirtualization agent; protecting the paravirtualization agent by obstructing the modulation of a memory region to which the paravirtualization agent is allocated; when file input-output is generated in the paravirtualization agent, transmitting information associated with the generated file input-output to a host-based file system protection service to inquire about accessibility; determining an authority for access to the generated file input-output through a reasoning engine in the host-based file system protection service; and transmitting a result of the determination to the paravirtualization agent, and processing the generated file input-output, thereby protecting a file in a file system.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: November 12, 2019
    Assignee: Soosan Int Co., LTD
    Inventors: Hyoung Bae Park, Hoi Chan Jeong, Seung Hyun Seo, Jun Young Park