Abstract: A power conversion system and power control method for reducing cross regulation effect uses a voltage feedback adjustment circuit to modulate an error signal fed back from an output voltage so as to predict the energy of an output corresponding to its load states. While the energy delivered to an output terminal with its load remaining the same does not change, the energy delivered to an output terminal with its load changing is adjusted accordingly. The power conversion system thus effectively reduces the cross regulation effect and obtains excellent steady system output and transient response.

Abstract: A disclosed constant voltage circuit is configured to become active or inactive and convert an input voltage applied to an input terminal into a predetermined constant voltage for output from an output terminal. The circuit includes an output transistor for supplying, from the input terminal to the output terminal, an output current, an error amplifier circuit unit for controlling operations of the output transistor to make a first proportional voltage, which is proportional to the output voltage from the output terminal, equal to a predetermined reference voltage, a ramp voltage generating circuit unit for generating and outputting a ramp voltage whose voltage level increases at a predetermined speed from start-up, and an amplifier circuit unit for amplifying the voltage difference between the ramp voltage and a second proportional voltage, which is proportional to the output voltage, and outputting the amplified voltage difference to a control electrode of the output transistor.

Abstract: A frequency limitation method used in quasi-resonant control of a switching regulator is disclosed. The switching frequency is limited through setting a minimum time limit, such as a minimum switching period or a minimum OFF time. The minimum time limit may be a first time limit or a second time limit. The minimum time limit is changed into another value if the minimum voltage point approaches the minimum time limit point, so as to eliminate the audible noise.

Abstract: The present invention discloses a power management chip with a dual function pin, the power management chip outputting pulse-width-modulation signals to control the switching of an up-gate transistor and a low-gate transistor for converting an input voltage to an output voltage, the up-gate and low-gate transistors being electrically connected to a node, the power management chip comprising: a dual function pin for electrically connecting with the input voltage or the node; a voltage sensing circuit electrically connected with the dual function pin for detecting the level of the input voltage; and a clock detection circuit electrically connected with the dual function pin for determining whether the signal received by the dual function pin is an oscillation signal.

Abstract: The present invention mainly relates to a current limiting circuit, also known as over-current protection circuit, and a power regulator using the same. The purpose for the circuit is to protect the power device and the loading circuit for the power regulator. The conventional current limiting circuit takes advantage of a resistor and a MOS to convert the detected over current into a voltage and then turn on a P-typed MOS to clamp the gate voltage of a power transistor so as to achieve the goal of current limiting. However, the process variation for the resistor and said MOS and their temperature variation lead to a significant error to the limiting current. The present invention, therefore, takes advantage of the current comparison to enhance the accuracy for the current limiting circuit.

Abstract: A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches.

Abstract: A technique for controlling a power supply with power supply control element with a tap element. An example power supply control element includes a power transistor that has first and second main terminals, a control terminal and a tap terminal. A control circuit is coupled to the control terminal. The tap terminal and the second main terminal of the power transistor are to control switching of the power transistor. The tap terminal is coupled to provide a signal to the control circuit substantially proportional to a voltage between the first and second main terminals when the voltage is less than a pinch off voltage. The tap terminal is coupled to provide a substantially constant voltage that is less than the voltage between the first and second main terminals to the control circuit when the voltage between the first and second main terminals is greater than the pinch-off voltage.

Abstract: A voltage regulator circuit and control method therefor. The circuit includes input and output terminals, an output transistor to pass a current from the input terminal to the output terminal according to a control signal, a reference voltage generator unit to generate and output a reference voltage, an output voltage detector unit to detect an output voltage output from the output terminal and generate and output a proportional voltage proportional to a detected voltage, a first error amplifier unit to control the output transistor to make the proportional voltage equal to the reference voltage, and a second error amplifier unit to respond to fluctuation in the output voltage faster than the first error amplifier unit and increase the output current from the output transistor for a period of time when the output voltage rapidly drops. Current consumption of the second error amplifier unit is changed according to the output current.

Abstract: A switching controller for a PFC converter is provided. The switching controller comprises a switching-control circuit, a current-command circuit, a programmable feedback circuit, a modulator, an over-voltage detection circuit, and a light-load detection circuit. The switching controller is capable of regulating a bulk voltage of the PFC converter at different levels in response to load conditions of the PFC converter. A turbo current eliminates a first voltage undershooting of the bulk voltage at the transient that the bulk voltage decreases to arrive at a second level from a first level. A voltage-loop error signal is maximized to eliminate a second voltage undershooting of the bulk voltage at the transient that the bulk voltage starts to increase toward the first level from the second level.

Abstract: As for a transistor, overlapped are factors such as a variation of a gate insulation film which occurs due to a difference of a manufacturing process and a substrate used and a variation of a crystalline state in a channel forming region and thereby, there occurs a variation of a threshold voltage and mobility of a transistor. This invention provides an electric circuit which used a rectification type device in which an electric current is generated only in a single direction, when an electric potential difference was applied to electrodes at both ends of the device. Then, the invention provides an electric circuit which utilized a fact that, when a signal voltage is inputted to one terminal of the rectification type device, an electric potential of the other terminal becomes an electric potential offset only by the threshold voltage of the rectification type device.

Abstract: In a grid-tie inverter, the DC input is phase and pulse-width modulated to define multiple phase shifted voltage pulses with the width of each pulse being modulated according to the grid AC amplitude for the corresponding portion of the AC phase.

Abstract: A multi-phase driving circuit includes a single-phase pulse-width modulation (PWM) controller, a number of drivers, and a number of switch circuits connected to the number of drivers correspondingly. The single-phase PWM controller is configured for providing a single-phase PWM signal. Each of the number of drivers receives the single-phase PWM signal and adjusts a phase of the single-phase PWM signal to output an adjusted PWM signal. Each of the number of drivers also outputs a driving signal. Each of the number of switch circuits receives the adjusted PWM signal and the driving signal from a driver. Each of the number of switch circuits generates a driving voltage controlled by the driving signal and adjusts a phase of the driving voltage controlled by the adjusted PWM signal and then outputs the adjusted driving voltage, so as to make the number of switch circuits output a multi-phase driving voltage to a load.

Abstract: A control system for a power inverter is disclosed. The power inverter may be configured to supply power to a grid. The control system may include a plurality of output voltage sensors and a plurality of output current sensors configured to measure output line voltages and output line currents of the power inverter. The control system may further include a controller coupled to the power inverter. The controller may be configured to provide a control signal associated with a disturbance frequency to the power inverter. The controller may be further configured to determine an output power of the power inverter based on the output line voltages and output line currents, and determine an amplitude of oscillation in the output power caused by the disturbance frequency. The controller may also be configured to detect an islanding condition, if the amplitude of oscillation is below a threshold.

Abstract: A power electronics power module is provided. The power electronics power module includes an electrically conductive substrate, a electronic die having first and second opposing surfaces and at least one transistor formed thereon, the electronic die being mounted to the electrically conductive substrate and the at least one transistor being configured such that when the at least one transistor is activated, current flows from the first surface of the electronic die into the electrically conductive substrate, and a control member at least partially imbedded in the electrically conductive substrate, the control member having a control conductor formed thereon and electrically connected to the at least one transistor such that when a control signal is provided to the control conductor, the at least one transistor is activated.

Abstract: A power conversion device includes input terminals, first output terminals, second output terminals, and an insulation transformer. The insulation transformer includes a primary coil and a secondary coil of equal inductance. The polarity of one end of the primary coil is same as the polarity of the other end of the secondary coil. One of the first output terminals is connected to an input terminal and the one end of the primary coil. The other of the first output terminals is connected to an input terminal and one end of the secondary coil. One of the second output terminals is connected to the other end of the primary coil and the other end of the secondary coil. The other of the second output terminals is connected to an input terminal.

Abstract: It is an object of the present invention to provide a rectifier circuit that can suppress deterioration or dielectric breakdown of a semiconductor element due to excessive current. A rectifier circuit of the present invention includes at least a first capacitor, a second capacitor, and a diode which are sequentially connected in series in a path which connects an input terminal and one of two output terminals, and a transistor. The second capacitor is connected between one of a source region and a drain region and a gate electrode of the transistor. Further, the other one of the source region and the drain region and the other one of two output terminals are connected each other.

Abstract: A powered device includes a first switch, a second switch, and a controller. The first switch is disposed between a center tap of the first transformer and a center tap of the third transformer. The second switch is disposed between a center tap of the second transformer and a center tap of the fourth transformer. The controller is coupled to the first switch and the second switch. The controller is constructed and arranged to output a control signal to the first and second switches to electrically connect the center taps of the first and third transformers together and concurrently electrically connect the center taps of the second and fourth transformers together. The powered device is constructed and arranged to operate in 4-pair mode when the center taps of the first and third transformers are connected together and the center taps of the second and fourth transformers are connected together.

Abstract: A controller for a power inverter having a gate assembly with an alternating current power output. A gate driver controls the activation of the gate assembly while a processor controls the operation of the gate driver. A current sensor has an output signal representative of the current at the power output. A noise detector circuit provides an output signal to the processor of the frequency of electromagnetic noise in the power inverter and the processor is programmed to sample the current from the current sensor at the frequency of the noise.

Abstract: An apparatus and a method for a bias modulator using a Zero Current Switching (ZCS) are provided. The bias modulator includes a Pulse Width Modulation (PWM) signal generator for converting an input envelope signal to a PWM signal; a PWM/ZCS converter for calculating the number of ZCS control signals to be provided within an on-time duration of the PWM signal and generating at least one ZCS control signal according to the number of the ZCS control signals; and a ZCS switching regulator for generating a bias current according to the ZCS control signal.

Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.