Patents Examined by Benjamin D. Driscoll
  • Patent number: 5850150
    Abstract: A final stage clock buffer for use in a clock distribution network in a circuit with scan design includes a demultiplexer circuit and a control circuit. The buffer receives an input clock signal and outputs a clock signal and a scan clock signal. The buffer can operate in a functional mode, a scan mode and a hold mode. The demultiplexer circuit receives the input clock signal and a scan enable signal. The scan enable signal, when asserted, causes the buffer to enter the scan mode. In the scan mode, the demultiplexer circuit propagates the input clock signal to a scan clock terminal and a constant logic level to a clock terminal. When the scan enable signal is deasserted, the demultiplexer circuit propagates the input clock signal to the clock terminal and a constant logic level to the scan clock terminal. The control circuit receives a chip-enable signal. When the chip-enable signal is asserted while the scan signal is deasserted, the buffer enters the functional mode.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: December 15, 1998
    Assignee: Sun Microsystems, Inc.
    Inventors: Sundari S. Mitra, Prasad H. Chalasani, Marc Elliot Levitt
  • Patent number: 5793225
    Abstract: A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.
    Type: Grant
    Filed: January 2, 1996
    Date of Patent: August 11, 1998
    Assignee: PMC-Sierra, Inc.
    Inventor: Brian Donald Gerson
  • Patent number: 5773994
    Abstract: An internal tri-state bus is provided in a field programmable gate array (FPGA). The FPGA is comprised of an input/output interface which receives input data and generates output data. User-configurable logic cells are included within the FPGA and are coupled to the input/output interface through interconnect elements. The interconnect elements provide a number of conductive elements which supply input signals to the logic cells and receive output signals generated by the logic cells. At least one of the logic cells contains at least one output and multiple logic elements which typically include AND gates, multiplexers and registers. The logic elements receive input signals from the interconnect elements, perform digital functions on the input signals and generate output signals to the interconnect elements. At least one logic cell in the FPGA contains a tri-state buffer which is coupled to at least one output of the logic cell.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: June 30, 1998
    Assignee: Cypress Semiconductor Corp.
    Inventor: Christopher W. Jones
  • Patent number: 5773996
    Abstract: A multiple-valued logic circuit includes a first device, a second device, a signal source, and a signal output terminal. The second device is connected in series with the first device. The signal source supplies an oscillating voltage across a series circuit consisting of the first device and the second device. The first device is constituted by at least one unit device having first and second main terminals and exhibiting voltage-current characteristics including negative differential resistance characteristics for obtaining a peak current between the first and second main terminals. The second device is constituted by at least two series-connected unit devices each having first and second main terminals and exhibiting voltage-current characteristics including variable negative differential resistance characteristics for obtaining a peak current changing between the first and second main terminals.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: June 30, 1998
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Waho Takao
  • Patent number: 5764080
    Abstract: In a programmable logic array integrated circuit device, various techniques are used to increase the flexibility with which the core logic of the device can be connected to the input and/or output pins of the device. While the techniques shown greatly increase circuit flexibility, they avoid the unnecessary overhead of interconnectivity which is completely general.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: June 9, 1998
    Assignee: Altera Corporation
    Inventors: Joseph Huang, Richard G. Cliff, Srinivas T. Reddy
  • Patent number: 5760607
    Abstract: A memory device controls the flow of data from the memory device to a configurable logic device. This is in contrast to circuits in which a configurable logic device generates a clock signal that controls the flow of data from a memory device to a configurable logic device. In one embodiment, the configurable logic device is a field programmable gate array ("FPGA"). The memory device can provide the configuration data on a serial output lead or a parallel data bus.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: June 2, 1998
    Assignee: Xilinx, Inc.
    Inventors: Kenneth E. Leeds, Charles R. Erickson
  • Patent number: 5760606
    Abstract: A switch circuit having a high withstanding voltage and low driving ability and another switch circuit having a low withstanding voltage and high driving ability are connected to a specified node in parallel. When discharging the charges of the specified node, the switch circuit having the high withstanding voltage is turned ON and the switch circuit having the great driving ability is then turned ON. Accordingly, it is sufficient that only the transition of the logical voltage of a switch circuit having the high withstanding voltage is taken into consideration to set the ON timing of a switch circuit having the high driving ability. Consequently, timing setting can be performed easily. After the switch circuit having the high driving ability is turned ON, a discharge path for the charges of the specified node takes two paths which passes through both switch circuits in parallel. Consequently, an operating speed can be increased.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: June 2, 1998
    Assignee: Matsushita Electric Industrial, Co.
    Inventors: Hiroshige Hirano, Shigeo Chaya, Toshiyuki Honda
  • Patent number: 5757206
    Abstract: An electronic device comprises a circuit that is provided with incrementally modifiable power consumption control means. By applying a program signal to this control means the balance between speed and power consumption is optimized. A PLA circuit considerably benefits from this architecture.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: May 26, 1998
    Assignee: Philips Electronics North America Corp.
    Inventors: Edward A. Burton, Farrell L. Ostler
  • Patent number: 5754058
    Abstract: An output buffer controlling circuit of a multibit integrated circuit is disclosed including: a pulse generating circuit for generating pulses by the combination of a first output enable signal and the output signal of an external sense amplifier; a high voltage sensing circuit for generating a high voltage sensing signal, when an input power voltage is high; and a delay circuit for generating a control signal for sequentially operating the output buffers in series so that the pulses generated from the pulse generating circuit have delay times different from one another according to the high voltage sensing signal generated from the high voltage sensing circuit.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: May 19, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Dae Young Moon, Gyu Suk Kim
  • Patent number: 5754062
    Abstract: First emitters of a pair of input multi-emitter transistors are connected to a current source in common, to form an input differential amplifier. The other emitters of the input multi-emitter transistors are connected to current sources respectively. Pull-up and pull-down transistors are provided for respective ones of a pair of output terminals. Bases of the pull-up transistors are supplied with collector voltages of the input multi-emitter transistors, while those of the pull-down transistors are supplied with voltages of the other emitters of the multi-emitter transistors. Provided is an emitter-coupled logic circuit which has excellent load drivability, operates stably and obtains complementary outputs at a low cost.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: May 19, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hisayasu Satoh, Kimio Ueda, Nagisa Sasaki
  • Patent number: 5754061
    Abstract: A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: May 19, 1998
    Assignee: Fujitsu Limited
    Inventors: Shinzou Satou, Kou Ebihara, Akiyoshi Suzuki, Keisuke Ishiwata, Kouji Miki, Hitoshi Ohmichi, Tamio Miyamura, Masamichi Kamiyama
  • Patent number: 5751165
    Abstract: A very high speed customizable logic array device comprising:a substrate having at least one gate layer and at least first, second and third metal layers formed thereon, the gate layer including a multiplicity of identical unit logic cells,the customizable logic array device including at least three of the following functionalities:NAND, NOR, inverter, AND and ORand further being characterized in that the ratio between the rise time and the fall time of the logic cells embodying each of the at least three functionalities is constant.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: May 12, 1998
    Assignee: Chip Express (Israel) Ltd.
    Inventors: Uzi Yoeli, Eran Rotem, Meir Janai, Zvi Orbach
  • Patent number: 5751161
    Abstract: A method and circuit are disclosed for changing the output impedance of an impedance controlled buffer from an initial impedance to a final impedance, while minimizing data transmission errors. The buffer has a plurality of impedance control inputs, with each of the plurality of impedance control inputs receiving a corresponding one of a plurality of bits of a binary coded impedance control signal. The output impedance of the buffer is controlled as a function of a value of the impedance control signal. First, the value of the impedance control signal is changed from an initial value corresponding to the initial output impedance to an intermediate value corresponding to an intermediate output impedance which is less than the initial output impedance. Next, the intermediate value of the impedance control signal is changed to a final value corresponding to the final output impedance.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: May 12, 1998
    Assignee: LSI Logic Corporation
    Inventors: Shuran Wei, Randall Bach
  • Patent number: 5751169
    Abstract: A fully differential, low voltage ECL gate (300) receives differential input signals (A, Ax, B, Bx) and provides them to first and second differential amplifiers (306, 328). The first differential amplifier (306) amplifies and level shifts the differential input (A, Ax) to provide a differential output (OUTx). The second differential amplifier amplifies the second differential input (B, Bx) to provide an amplified output, OUT. The amplified output signal, OUT, provides a different voltage level than that provided by amplified level shifted output signal, OUTx. The amplified level shifted output (OUTx) of the first differential amplifier (306) is then compared to the amplified output (OUT) of the second differential amplifier (328) to provide either an AND gate or an OR gate function.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: May 12, 1998
    Assignee: Motorola, Inc.
    Inventor: Pierce V. Keating
  • Patent number: 5748009
    Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: May 5, 1998
    Assignee: International Business Machines Corporation
    Inventors: Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph Andrew Iadanza, Frank Ray Keyser, Eric Ernest Millham, Timothy Shawn Reny, Brian A. Worth, Gulson Yasar, Terrance John Zittritsch
  • Patent number: 5744978
    Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: April 28, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Gary R. Gilliam, Steve G. Renfro, Kacey Cutler, Roland Ochoa, Craig E. Schneider
  • Patent number: 5742178
    Abstract: In a programmable logic device having a plurality of external pins each of which may be driven by an output drive structure controlled by a programmable logic block, a logic device such as an OR gate or a programmable pull-up or pull-down switch is inserted between the input terminal of the output drive structure and the programmable logic block or other internal logic block which controls the output driver. This inserted structure allows the macrocell to be used for internal logic while the output drive structure is used to stabilize power or ground voltage.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: April 21, 1998
    Assignee: Xilinx, Inc.
    Inventors: Jesse H. Jenkins, IV, Nicholas Kucharewski, Jr., David Chiang
  • Patent number: 5736866
    Abstract: Fast fall time for ECL logic waveforms are produced by use of a circuit, which very quickly transfers charge from the ECL output load capacitance into a temporary holding capacitor. The charge transferred onto the temporary holding capacitor may then be removed at a leisurely pace. The circuit includes a pulldown transistor, and a control circuit that selectively turns the pulldown transistor on, if the ECL output will be low, or off, if the ECL output will be high. The control circuit includes an emitter-follower transistor which follows the differential ECL collector node that changes voltage inversely to the desired final ECL output. A diode is connected to the emitter-follower transistor's emitter so that the diode output is two diode drops below the ECL collector node inverse in polarity to the output. The diode drives the base of the pulldown transistor, so that the base of the pulldown transistor remains static until the inputs to the circuit change.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: April 7, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jerome D. Harr
  • Patent number: 5736870
    Abstract: A bidirectional bus circuit according to the present invention typically includes: (a) a first and a second bus line portion for carrying a bidirectional bus signal, where the first bus line portion has a first and a second end, and the second bus line portion has a third and a fourth end; (b) a bus direction sense line for carrying a bus direction signal; (c) a sensing circuit coupled to the sense line for detecting the bus direction signal; and (d) a driving circuit coupled to the sensing circuit and coupled between the second end of the first bus line portion and the third end of the second bus line portion for driving the first and second bus line portions. According to one embodiment of the present invention, the sensing circuit may include a cross coupled NAND gate latch or a cross coupled NOR gate latch. The driving circuit may include a first buffer circuit for driving the first bus line portion and a second buffer circuit for driving the second bus line portion.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: April 7, 1998
    Assignee: Intel Corporation
    Inventors: Jeffrey K. Greason, James P. Kolousek
  • Patent number: 5731717
    Abstract: A single-electron tunneling (SET) element used as a logic or memory element includes at least one tunneling junction with a minute metal-insulator-metal sandwich structure, and a biasing power source which is connected in series to the at least one tunneling junction and whose ON/OFF operation is controlled by an external control input. SET oscillations are generated in the at least one tunneling junction and the generated oscillations are phase-locked to subharmonics of a pump signal supplied from an AC power source, to thus exhibit a plurality of stable phase states. Also, a plurality of gates, each including the SET element, are constituted in the form of a logic network to realize a predetermined logic operation in a computer. In the logic network, an input signal with a frequency half that of the pump signal is continually applied to a specified gate among the plurality of gates, while the biasing power sources of all of the gates are kept in ON state.
    Type: Grant
    Filed: April 5, 1996
    Date of Patent: March 24, 1998
    Assignee: Fujitsu Limited
    Inventors: Toshio Ohshima, Richard A. Kiehl