Abstract: A logic gate circuit includes a resistor, a current limiting circuit, a switching transistor, and a load transistor, the source of load transistor being connected to the drain of the switching transistor, the gate of the switching transistor being connected to an input terminal, the resistor being connected between the source of and the gate of the load transistor, and the current limiting circuit being connected between the gate of the load transistor and the source of the switching transistor. By using this logic gate circuit in the low speed operating section of an LSI, the dissipation current and the chip area of the LSI can be reduced even when the gate width and the threshold voltage of the load FET are the same as those in the high speed operating section.

Abstract: A current type inverter circuit or the like is obtained which operates at a high speed with a low power consumption. A reference power source 1 has one end connected to a power source VDD and the other source receiving a reference current Iref. A drain and a gate of an NMOS transistor Q1 of a current mirror circuit CM1, as an input part, receive an input current Iin. A drain of an NMOS transistor Q2 is connected to an node N1 of the other end side of the reference power source 1 as an output part. As an input part, a drain and a gate of an NMOS transistor Q3 of a current mirror circuit CM2 are connected to the node N1 while a drain of an NMOS transistor Q4 functions as an output part for outputting an output current Iout. The transistors are set so that all of the conditions TS1.gtoreq.1, TS2.gtoreq.1 and TS1.multidot.

Abstract: An output buffer circuit with low power pre-output driving capability uses existing output drivers and includes input inverters with three-state outputs interposed between the input and output stages and a feedback circuit with three-state outputs connected to the output stage. During normal data transmission, the input inverters buffer the incoming complementary data signals driving the pull-up and pull-down transistors in the output stage while the three-state outputs of the feedback circuit are turned off. Upon receiving an active pre-output control signal, the input inverters are disabled, thereby isolating the pull-up and pull-down transistors from the incoming complementary data signals, and the feedback circuit is enabled. The enabled feedback circuit monitors the signal level of the output signal from the output stage.

Abstract: A static logic circuit employs pull-down type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities higher than those of the logic transistors forming the power supply current path, and pull-up type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities lower than the logic transistors forming the power supply current path, and comprises logic series formed by alternately cascading the two types of the logic gates. The static logic circuit is provided with signal merged logic circuits each of which provides a signal having a high speed falling transient and a high speed rising transient by merging the output signals of the logic series.

Abstract: A semiconductor integrated circuit device having an input/output circuit for inputting and outputting data having a GTL level includes a pull-down output MOSFET (Q1) and a pull-up output MOSFET (Q2) both electrically connected to an input/output terminal and a gate drive signal generating circuit (DPG) electrically coupled to the gate of the pull-up output MOSFET (Q2). Upon data transmission, the gate drive signal generating circuit (DPG) controls the operation of the output MOSFET (Q2) so that the output MOSFETs (Q1 and Q2) are contemporarily brought into an ON or OFF state according to data to be transmitted. On the other hand, upon data reception, the gate drive signal generating circuit (DPG) forms a control pulse for temporarily turning ON one of the output MOSFETS (Q2) immediately after high-level data has been received, and supplies it to a gate terminal of the output MOSFET (Q2).

Abstract: A data signal is input into an integrated circuit and the data signal is transmitted through a series of logic gates that cause a propagation delay. An external clock line associated with the data signal is also inputted into the integrated circuit. The external clock signal is passed through a delay shifter that adds a controllable amount of delay to the clock signal. The amount of delay added to the clock signal should equal the total amount of propagation delay added to the data signal. The clock signal is then also transmitted through a phase-lock loop to stabilize the clock signal. The delayed internal clock signal is then used to clock the data signal which has been transmitted through a series of logic gates that have added propagation delay. Since the internal clock signal has been delayed an equal amount as the data signal, the data signal will be clocked at an appropriate time.

Abstract: Dynamic CMOS circuits are provided with improved noise immunity. These circuits comprise first and second stacked NFET devices connected respectively between ground and a first node. An input node is coupled to the first NFET device closest to ground and a clock node coupled to the second NFET device closest to the first node. A PFET device is connected between the input node and a node formed by the stacked NFET devices. The first NFET device and the PFET device form an inverter for receiving an input signal, the switch point of the inverter being adjustable by adjusting the PFET/NFET ratio of the inverter, thereby increasing the noise immunity of the circuit.

Abstract: Bus control circuitry for enabling/disabling the drivers of a bus in an integrated circuit is presented. The bus control circuitry has master control signal logic blocks and output enable blocks. The bus control circuitry enables one and only one bus driver set at a time to avoid bus contention. Furthermore, the bus driver circuits are enabled and disabled with precise timing to avoid even momentary bus contention. Finally, the bus, driver circuits and control circuitry may be tested with serial scanning.

Abstract: To obtain a semiconductor integrated circuit reduced in hardware size, by avoiding duplication of a common constitution. A logic block (100) comprises logic means (A), logic means (B), and logic means (C), and the output of a pipeline register (11) is connected to the logic means (A) through a signal line (a), and the logic means (A) and logic means (B) are connected through a signal line (b). The logic means (A) is also connected to the logic means (C) through a signal line (c), and the logic means (C) is connected to the input of a pipeline register (21) through a signal line (d). When performing the same logic action in the first half period and second half period of a clock signal, it is not necessary to install two identical logic means, so that the size of the hardware may be reduced as compared with the constitution of installing two identical logic means.

Abstract: A semiconductor device having an output circuit includes a first field-effect transistor having a source connected to a line from which a first voltage is inputted, and a second field-effect transistor having a source connected to a drain of the first field-effect transistor, a gate connected to a data line from which a level signal is inputted, and a drain connected to an output terminal to which an output signal is outputted. A control unit controls a voltage at a gate of the first field-effect transistor when the second field-effect transistor is in ON state, so that a voltage at the drain of the second field-effect transistor is equal to a second voltage.

Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g.

Abstract: A stable output can be obtained with respect to the input level fluctuations. Two impedance elements 1 and 2 each having a single-electron tunnel junction are connected in series. The tunnel resistances R.sub.1 and R.sub.2 and the junction capacitances C.sub.1 and C.sub.2 of the respective impedance elements 1 and 2 are determined as R.sub.1 >R.sub.2 and C.sub.1 .gtoreq.C.sub.2 or R.sub.1 <R.sub.2 and C.sub.1 .gtoreq.C.sub.2. By this, the charge stored on the island portion 4 can be quantized at a roughly integral value times the prime charge e according to the input voltage, the current-voltage characteristics represent Coulomb staircase, a square-shaped Coulomb oscillation characteristics can be obtained, and a constant output current value to an input voltage range with constant width can be obtained, so that it is possible to widen the voltage margin corresponding to the respective input logical level. A stable output can be obtained against the input voltage fluctuations.

Abstract: An integrated circuit output section has a controller that controls a plurality of drivers to transmit data signals over output lines in a group staggered manner to substantially reduce the generation of inductive noise or ground and power bounce. The controller staggers the transmission of the data signals in each group relative to the other groups to achieve a reduction in inductive noise of greater than 25% using relatively short total staggering times of less than five times the transition switching time of a driver for the groups of data signals. Also, an enhanced reduction in inductive noise is achieved with a total staggering time equal to or less than a driver transition switching time, wherein at least one group has a different number of data signals than the other groups.

Abstract: An apparatus and method for providing short circuit current free dynamic logic building blocks comprising P-logic and N-logic dynamic domino building blocks having separate clocks for driving the P-logic and N-logic evaluate and pre-charge stages. The P-logic building gates are pre-charged to a zero volt output and upon the transition from high to low on the input line, will provide a high output during the evaluation cycle. Conversely, the N-logic building blocks are pre-charged with a high output level and upon the transition of a low to high input to the building block device, will provide a low output signal during the evaluation period. Both building block types are pre-charged again at the end of the evaluation period to provide an inherently glitch-free dynamic logic device. Separate evaluate and charge clock signals are provided to each of the P-logic and N-logic building blocks which are configured to provide a non-overlapping charge and evaluation cycle.

Abstract: A clock generator comprising inverters I.sub.1A, I.sub.1B, I.sub.2A, a NOR circuit NO.sub.1, an inverter I.sub.3A and a NOR circuit NO.sub.2 . . . which transmit sequentially an input clock signal A, D flip-flops DF.sub.1, DF.sub.2, DF.sub.3 . . . which latches the input clock signal at different positions during transmission, NAND circuits N.sub.1, N.sub.2, N.sub.3 . . . which output intermediate signals A1, A2, A3 . . . in response to latch data of the D flip-flops DF.sub.1 DF.sub.2, DF.sub.3 . . . and the input clock signal, and a multi-input AND circuit AN.sub.0 to which the intermediate signals A1, A2, A3 are inputted, and being configured so as to input each signal based on the latch data of adjacent D flip-flops to the NOR circuits NO.sub.1 and NO.sub.2, thereby duty of an output clock signal generated based on the input clock signal does not become small even when the input clock signal having high frequency is inputted.

Abstract: A mechanism is provided for allowing input/output signal routing along the periphery of a programmable integrated circuit (IC) so that uniform circuit usage across the programmable integrated circuit is allowed in conjunction with predetermined pin assignments. The mechanism includes a plurality of periphery interconnect lines that run along the periphery of a programmable IC. Input/output blocks (IOBs) that are similarly along the periphery of the programmable IC and configurable logic blocks (CLBs) are coupled to the plurality of periphery interconnect lines using a programmable local interconnect structure. Each IOB includes an associated pad and an input/output external pin. Individual segments of the plurality of periphery interconnect lines utilize a bi-directional buffer to buffer a line of the periphery interconnect.

Abstract: An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.

Abstract: A signal receiver for an interface of an MPU or a memory has a differential amplifier for receiving an input signal from an input/output line for the IPU and the memory, an inverter for receiving the output of the differential amplifier, and a feed-back section for providing the signal receiver with a transfer characteristic having a hysteresis with respect to the input signal of tile signal receiver. The feed-back section includes a feed-back signal path and a feed-back current path formed between a supply line and the output of the differential amplifier. The output signal of the gate is feed-backed to the feed-back current path as a control signal for making the feed-back current path active or inactive to shift tile voltage level of the output of the differential amplifier. The gate is not operated by a transient oscillation of the input signal so that unnecessary power consumption due to tile transient oscillation of the input of tile signal receiver is avoided.

Abstract: A technique is described for transmitting events over three or more conductors in which a sequence of activity of the conductors for information transfer is provided. To transfer information, the conductors are placed in an active state in a sequential manner, and then returned to an inactive state after each has been active in a time period short enough to prevent all conductors from being active at the same time.

Abstract: Multiple in-system programmable devices are connected in series to a programming controller for simultaneous programming. One embodiment puts all such in-system programmable devices in programming mode, and to receive programming data and programming instruction simultaneously. In that configuration, all devices begins programming and stops programming simultaneously.