Abstract: An IC chip employs a common multiplexor logic element in different logic configurations for performing a variety of different logic functions, whereby path delays can be accurately matched. In addition, a phase-locked-loop is employed for providing accurately timed signals having different durations and differently occurring timing edges.

Abstract: A programmable logic device (PLD) integrated circuit containing an array of fuse or anti-fuse links includes verification circuitry configured to classify link resistances after programing into three resistance zones, corresponding to a "closed" state zone, an "open" state zone and a "forbidden" state zone intermediate the "closed" and "open" state zones. Two reference resistance values, namely a lower reference resistance value and the higher reference resistance value, divide the entire range of possible link resistance values into the aforementioned three resistance zones. Because the ratio between the higher reference resistance value and the lower reference resistance value is typically more than 50, the verification circuitry includes a switchable two level current source that produces a voltage across the link of correct dynamic range.

Abstract: In an output buffer circuit so configured that a capacitor connected to a gate of an output driving MOS transistor and including a gate capacitance of the output driving MOS transistor is gradually charged through a resistor, so as to realize a slow rising or falling time, there is additionally provided a threshold voltage charging circuit for rapidly charging the capacitor to a threshold voltage level of the output driving MOS transistor when the output driving MOS transistor is to be turned on. With this arrangement, the propagation delay time of an output voltage can be minimized.

Abstract: A data output buffer circuit for a semiconductor device for transferring read cell data to the peripheral circuits, comprising an input terminal for inputting the read cell data, a first NMOS transistor for transferring the data from the input terminal when it has a first logic level, a first PMOS transistor for transferring the data from the input terminal when it has a second logic level, a second PMOS transistor for transferring a high logic signal in response to an output signal from the first NMOS transistor, a second NMOS transistor for transferring a low logic signal in response to an output signal from the first PMOS transistor, and an output terminal for outputting the high logic signal from the second PMOS transistor or the low logic signal from the second NMOS transistor to the peripheral circuits.

Abstract: A means of converting low voltage CMOS logic levels operating with a 3.3 volts logic level to low voltage PECL logic levels operating with a 3.3 volts supply voltage and a 0.8 volts logic level. The circuit design is process insensitive, and the characteristics of the converter emulate the emitter follower outputs of ECL devices. The converter solves the signal ringing problems caused by open output conditions, and is less susceptible to electromagnetic interference.

Abstract: An output buffer circuit operating normally when its supply potential is exceeded by the potential of the bus to which the buffer circuit output is connected. The circuit comprises a p-channel MOS transistor and a first and a second n-channel MOS transistor. The output node of the output buffer circuit is connected not to the p-channel MOS transistor but to the connection point between the source of the first n-channel MOS transistor and the drain of the second n-channel MOS transistor. The threshold potential of the first n-channel MOS transistor is set so that, with the output node in the high-impedance state, the first n-channel MOS transistor is turned off when the output node potential exceeds the supply potential of the output buffer circuit. This prevents the p-channel MOS transistor from getting activated or from being forward-biased between the back gate and the drain or source. Thus no leak current flows when the bus potential becomes higher than the supply potential of the output buffer circuit.

Abstract: A programmable interconnection system for a programmable array includes pluralities of parallel buses for rows and columns of logic cells arranged in the array. Two groups of seven buses are provided for each row or column of logic cells. The buses include conductors connectable to each other, and selectively connectable to, or isolated from, the logic cells. A hierarchy of conductor lengths is disclosed to provide intra-sector and inter-sector bussing. Staggered switching is employed for adjacent sector access.

Abstract: An input stage of a level converter for converting an ECL compatible signal to an MOS compatible signal is formed as a differential amplifier. The differential amplifier produces a current that is coupled directly to a first transistor of a pair of complementary transistors, during a transition interval, to turn on the first transistor. An output signal of the first transistor is fed back to a control terminal of the first transistor via a first inverter. Consequently, the first transistor is actively turned off immediately following the transition interval. A second inverter and the first inverter form a latch for maintaining the output signal unchanged, after the first transistor is turned off.

Abstract: An output driver circuit for a semiconductor chip has a push-pull output with a P-channel pull-up and an N-channel pull-down. Predrivers produce push-pull outputs for driving the gates of the output driver. Compensator circuits, one for the N-channel pull-down, and one for the P-channel pull-up, are used to prevent the transition from high-to-low or low-to-high from being too rapid, which could cause noise due to inductance of the package leads. A feedback circuit halts the operation of the compensator circuits after a short interval. An overvoltage circuit formed in a well of the semiconductor chip holding the driver circuit, having an input coupled to receive the data output of the predriver circuit going to the P-channel pull-up, also functions to prevent damage to the output driver circuit due to overvoltage on the output node.

Abstract: An input/output architecture for a field-programmable gate array integrated circuit including a plurality of logic function modules in an array of rows and columns, each of the modules having at least one input conductor and at least one output conductor; a plurality of interconnect conductors, comprising a plurality of input/output pads; a plurality of input/output kernels, each input/output kernel comprising an input buffer having a data input connected to one of the I/O pads and a data output connected to an input buffer data conductor, an output buffer having a data input connected to an output buffer data conductor, a data output connected to the I/O pad, and an enable input connected to an output buffer enable conductor; the input buffer data conductors extending in either the row or the column direction, different ones of the input buffer data conductors extending different numbers of rows or columns, the input buffer data conductors forming first intersections with inputs of the modules; the output bu

Abstract: A method and apparatus for a circuit physically realizing a CMOS buffer with a controlled slew rate at the output and using no additional standby power to achieve the slew rate control is described. A feedback path from the output is coupled to transistors comprising a differential pair, the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback path to control the high-to-low and low-to high transition rate of the output. The circuit of the invention allows a system designer to construct a buffer for driving a bus with excellent on chip and bus signal noise characteristics using standard digital CMOS technology and having excellent standby and active power characteristics. An open drain buffer and a push-pull buffer are described. An integrated circuit implementing application logic coupled to input/output and output buffers embodying this circuit is disclosed.

Abstract: An integrated circuit with programmable output drive/program pins includes a plurality of output pads (30) which are each operable to interface with a separate and dedicated output driver (38). The output driver (38) is operable to drive an LED output device (14) in an operating mode. In a program mode, the driver (38) is disabled and a program buffer (40) enabled. At the same time, the LED output device (14) is disabled such that no impedance is presented to the output pad (30) due to operation of the LED output device (14). A programming resistor (18) is disposed between the pad (30) and one of three program reference voltages. A first program state is represented when the resistor (18) is tied to ground, a second program state is represented when the resistor (18) is tied to an open circuit and a third program state is represented when the resistor (18) is tied to a positive voltage.

Abstract: In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.

Abstract: The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix and a programmable centralized switch matrix. Each programmable logic block is coupled to a plurality of programmable I/O macrocells by an output switch matrix. Each programmable I/O macrocell is connected to one of a plurality of I/O pins for the programmable logic block. In one embodiment, an input macrocell couples an I/O macrocell and the associated I/O pin to the programmable input switch matrix. The programmable input switch matrix provides a uniform treatment of all feedback signals to the programmable centralized switch matrix and thereby simplifies signal routing, provides an improved functionality balance, and improved resource utilization within the PLD. The output switch matrix routes output signals from a programmable logic block to any one of a multiplicity of the I/O macrocells.

Abstract: The gates (11) of the exclusive OR type having two inputs (A, B) are disposed in tree structure in successive layers of an integrated circuit beginning with an input layer which receives the input signals of the tree. The output of each gate is connected to an input of a gate in the adjacent layer. Each gate includes two cells (11a, 11b) that switch substantially simultaneously in response to two respective complementary signals (A, NA; B, NB) from one of the two inputs and that supply respective output signals that are representative of the complementary functions (XOR, NXOR) of the exclusive OR type. This makes it possible to obtain propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagated may be.

Abstract: A latch circuit employs state-walk logic that makes the transition from "set" to "latched" states without the need for multiple phases, critical timing or introduction of extra periods into any timings to account for worst case scenarios. The has particular application to row address receivers for dynamic random access memories (DRAMs) and, in its basic form, comprises a pair of identical receiver circuits of opposite logic state when off, with clock and data inputs and true and complementary outputs. The receivers are turned on by an activating clock signal. When the receivers are enabled, address data is evaluated as soon as it is received causing the latch to be set. This is the first step in the "state walk" of the latch. The outputs of the latch are fed back to turn off the receiver circuits completing the second step of the "state walk". The circuit now ignores any changes in the input address data, thus latching the input data.

Abstract: Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

Abstract: A trinary input logic gate (25). A first output transistor (36) is coupled to a first voltage output (Vo1) and pulls the voltage output to a high voltage in response to a voltage input (VIN) below a defined low threshold. A second output transistor (35) is coupled to a second voltage output (Vo2) and pulls the second voltage output to a low voltage in response to a voltage input above a defined high threshold. Swing limiting circuitry (28, 26) is coupled to the gates of both the first and second output transistors, and when the voltage input is between the defined thresholds, the swing limiting circuitry operates to keep the gates of the first and second output transistors within a middle range of defined thresholds such that both output transistors are enabled, and therefore the first and second voltage outputs are at opposite polarities. When the input voltage is above the high threshold, both outputs are at a low voltage.

Abstract: A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A general interconnect structure (20, 30) is provided for interconnecting a LAB with other LABs. A LAB-based interconnect structure (24, 26) is provided for connecting inputs of the LEs in a LAB to a subset of the general interconnect. One or more of output signal lines (55) are included in the LAB-based interconnect structure and are connectable to device output pins. A digital information processing system incorporating the invention is disclosed.

Abstract: An emitter-coupled logic circuit having superior drivability, stable operation, and obtaining complementary outputs. A pair of input differential transistors have their emitters coupled to a first current source in common, their bases connected to receive respective input signals, and outputting complementary logic values corresponding to the respective input signals. Pull-up and pull-down transistors are provided for respective ones of a pair of output terminals. Bases of the pull-up transistors are supplied with collector voltages of the input transistors and their emitters are connected to the respective output terminals. The bases of the pull-down transistors are supplied with the respective input signals, their emitters are coupled to a second current source in common, and their collectors are connected to the respective output terminals. A stabilizing circuit is connected to the respective output terminals to maintain the pull-up transistors in conducting states.