Abstract: A master clock signal, used to operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or that communicate such signals to a destination external to the integrated circuit.

Abstract: A word line driver circuit for use in a semiconductor memory device for driving a word line of the memory device to a word line driving voltage having a voltage level greater than that of a power supply voltage includes a control circuit and a word line driving circuit. The word line driving circuit includes a pull-up transistor which is connected in series between the word line driving voltage and the word line, a transfer transistor connected in series between a row decoding signal and the gate electrode of the pull-up transistor. The control circuit generates a transfer output signal which is applied to the gate electrode of the transfer transistor. In a first operating mode, the transfer output signal has a voltage level greater than the power supply voltage by an amount equal to the threshold voltage of the transfer transistor, and, in a second operating mode, the transfer output signal has a voltage level equal to the power supply voltage.

Abstract: A driver for providing binary signals from a data system to a transmission line is disclosed. The driver includes a first field-effect transistor (FET) coupled between an output node and ground for conducting current from the output node to ground. The output node is connectable to the transmission line. An initial charging stage provides an initial charging current to the gate of the first FET for a period of time not to exceed an initial charging time period. The initial charging time period has a length approximately equal to a period of time necessary to increase the gate voltage of the first FET from ground to the threshold voltage of the first FET. A main charging stage provides a main charging current to the gate of the first FET for a period of time not to exceed a main charging time period. A discharging stage provides a discharging current from the gate of the first FET to ground.

Abstract: A reprogrammable logic device and method of operation. The logic device is divided into a first hemisphere 101 and a second hemisphere 102. The first and second hemispheres of the arrays are internally connected by horizontal 20 and vertical 22 conductors. A global interconnect array 107 is placed between the hemispheres and is used to selectively connect the horizontal conductors of the hemispheres.

Abstract: A translator circuit for converting from a first logic-level range to a second logic-level range, as is generally involved in the translation from an ECL stage to a CMOS stage. The translator includes a reference stage that provides a reference voltage that is coupled to the CMOS logic stage as well as the ECL logic stage. The ECL logic stage is indirectly coupled between a high potential power rail and a low potential power rail through a plurality of transistors. The CMOS stage is coupled to the ECL stage through two emitter-follower transistors. The CMOS stage uses current-mirroring techniques in combination with the isolated reference stage to effect a translation from the ECL logic level to the CMOS logic level. The CMOS stage also provides relatively fast propagation time which may be set, within certain limits, to a desired time.

Abstract: A video and audio signal recording apparatus for recording video and audio signals on parallel tracks formed on a recording medium, includes: a divider for dividing a video signal into video signal blocks each contained in a unit period which is N times (N=1, 2, . . .) as long as one field period of the video signal; another divider for dividing an audio signal into audio signal blocks each contained in a specific period which is synchronized with the unit period; and a recorder for recording signal contained in each of said video signal and audio signal blocks in each of fully independent areas on the recording medium such that any two of the fully independent areas adjacent to each other in a track width direction are separated from each other by an unrecorded area composed of L unrecorded consecutive tracks (L=1, 2, . . .

Abstract: A k-fault tolerant AND gate circuit comprises k+1 levels and the input level comprises k+1 AND gates. Embodiments provide intermediate levels arranged for providing a two-fault tolerant AND gate circuit and a four-fault tolerant AND gate circuit, respectively.

Abstract: The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells.

Abstract: A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface. The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other. The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system. At a lowest level, each sector includes a plurality of logic elements. The logic elements are interconnected by a sector bus system. The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system.

Abstract: The basic building block of the invention is an inverter gate consisting of two stages: The first stage is an input logic switching stage consisting of a depletion mode pull-up FET whose gate is the input node and whose source-to-drain channel is connected in series through a level-shifting Schottky diode with the source-to-drain channel of an depletion mode pull-down FET between drain and source voltage rails. The source of the pull-up FET is connected to the diode's anode while the drain of the pull-down FET is connected to the diode's cathode and is the output node of the input logic switching stage. The level-shifting diode isolates the output node from the input node, which allows the input voltage to switch rail-to-rail without causing problems.

Abstract: An integrated circuit, supplied with a supply voltage Vcc, the intergrated circuit including: an antifuse including terminals; and a programming circuit for programming the antifuse, the programming circuit using a programming voltage Vpp that is substantially higher than the supply voltage Vcc, wherein the programming circuit including structure to apply the supply voltage Vcc to the terminals of the antifuse immediately after an application of the programming voltage Vpp to the terminals of the antifuse so that programming of the antifuse is not interrupted.

Abstract: A unique configuration control mechanism is disclosed which provides a fault-free verification of digital hardware and software modules, as well as verification of the logic control circuits used to drive said modules.

Abstract: A control circuit inhibits the CLOCK input to the CPU during power-up to prevent newer submicron CPUs from locking up during a power-up condition. The control circuit also provides a delayed control signal representing that the power supply has stabilized. This delayed control signal is used to consistently control the RESET signal.

Abstract: A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array blocks include CMOS look up table based logic modules that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.

Abstract: An interface circuit includes first and second MOS transistors of depletion type, first and second switching elements, and a control circuit. The current path of the first MOS transistor is connected between an output node of a MOS circuit formed in a semiconductor substrate and an output terminal and the gate thereof is connected to a power supply. The first switching element is connected between the backgate of the first MOS transistor and a ground terminal. The second switching element and the current path of the second MOS transistor are serially connected between the backgate of the first MOS transistor and the output terminal. The gate of the second MOS transistor is connected to the power supply and the backgate thereof is connected to the backgate of the first MOS transistor. The first and second switching elements are set into complementary states according to an output of the MOS circuit in response to an output signal of the control circuit.

Abstract: A dynamic decoder stores decoded signals in latch circuits for producing output signals, and the latch circuits are disabled after storing the decoded signals so that the output signals are free from undesirable level change of the decoded signals due to leakage between the dynamic decoding operations.

Abstract: A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.

Abstract: A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to produce a desired level of n-channel and p-channel drive at the pad. The nonselected p-channel FETs are maintained in a disabled condition by tieing them off to one side of a p-channel FET which is also connected to a n-type island in a substrate in which the circuit is formed. Electrostatic charge is drained from the gates of the disabled FETs through the n-type island when power is not applied to the integrated circuit thereby preventing failure of leakage tests. The nonselected n-channel FETs are similarly tied to one side of an n-channel FET which in turn is tied to a p-type island to achieve the same purpose for the n-channel FETs.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accomplish this, programming and data input signals that would normally go to the defective logic group are redirected to another logic group. The data output signals of the other group are substituted for the data output signals of the logic group that would normally have received the programming and data input signals that were redirected to the other logic group.