Abstract: An improved architecture and method of operation for providing redundancy in programmable logic devices. Spare columns or rows of logic blocks 115 and switch boxes 140 are employed to replace columns or rows of logic blocks containing one or more defective logic blocks. Associated logic enable the device to bypass a column or row of logic blocks 115 containing one or more defective logic blocks 115 and to switch in a spare column or row of defect-free logic blocks 115 as replacement.

Abstract: A method and apparatus for reducing aperture uncertainty and kick-back noise in high speed comparators is disclosed. The disclosed method is used in a comparator for comparing a first signal (INP) and a second signal (INM) and having a track mode and a regenerative mode of operation. The steps of this method are as follows. A first input current representing the first signal is switched through a first output node (OUTP) during the track mode and a second input current representing the second signal is switched through a second output node (OUTM) during the track mode. During the regenerative mode, approximately half of the first input current is switched through the first output node (OUTP) and approximately half of the first input current is switched through the second output node (OUTM). Also during the regenerative mode, approximately half of the second input current is switched through the first output node and approximately half of the second input current is switched through the second output node.

Abstract: A BICMOS output buffer circuit (20) has a voltage converter (21), a reference voltage circuit (28), a driver circuit (24), and a clamping circuit (40). The reference voltage circuit (28) receives a regulated voltage and provides a reference voltage having a low voltage level and a high voltage level. The low voltage level and the high voltage level control the logic high voltage of an output data signal. During a transition from a logic low voltage to a logic high voltage of the output data signal, the output data signal is allowed to overshoot the low voltage level. After the transition is complete, the output data signal settles at the high voltage level. This limits the amount of overshoot of the output data signal. The clamping circuit (40) dampens the oscillations of the output signal.

Abstract: A CMOS inverter circuit is provided which includes a compensation circuit which modifies the input threshold of the inverter depending on changes in the supply voltage. The inverter includes a standard CMOS inverter, current boosting circuitry and a further inverter. The input of the inverter is coupled to the current boosting circuitry and the input of the further inverter. The current boosting circuitry is also coupled to one of the supply voltages. The current boosting circuitry is operative to effectively change the PMOS to NMOS ratio of the inverter to maintain a substantially constant input threshold to counter the effect of any change in supply voltage.

Abstract: To facilitate the simultaneous programming of multiple antifuses on an integrated circuit, a first current path is established from a first programming terminal (VPP1) of a programmable logic device through a first antifuse to be programmed and a second current path is established from a second programming terminal (VPP2) of the programmable logic device through a second antifuse to be programmed. By supplying the programming current for programming the first antifuse from a different terminal than the programming current for programming the second antifuse, the two antifuses can be programmed simultaneously with an adequate amount of programming current being supplied to each antifuse. A programming current multiplexer circuit is disclosed for selectively coupling either a first programming voltage (VPP1) terminal, a second programming voltage (VPP2), or a ground terminal (GND) to a programming bus and/or to an antifuse to be programmed.

Abstract: A disturbance immune output buffer is disclosed. The output buffer includes a switch stage and a hold stage. The switch stage utilizes a pull-up transistor coupled to a switch power node and a pull-down transistor coupled to a switch ground node to drive a weak signal from internal circuitry to a corresponding strong signal on an output node. The pull-up transistor and pull-down transistor are then shut off. The hold stage utilizes a pull-up transistor coupled to a hold power node and a pull-down transistor coupled to a hold ground node to maintain the signal on the output node. As a result, a constant output signal is generated which is not effected by disturbances such as transients and noise associated with ground bounce. In addition, since the switch stage transistors are shut off, any ground bounce produced during state transitions of coupled output buffers will not effect sensitive circuit elements.

Abstract: A field programmable gate array (FPGA) configuration circuit reads configuration data from a memory (12) and converts the parallel data to a serial data stream through a shift register (16) clocked by a clock signal. A first FPGA (18) controls the serial data stream by providing the clock signal when enabled by a start signal. Once the configuration data has been completely loaded into the first FPGA, the first FPGA outputs a done signal to a second FPGA (20) to enable it's clock to control the serial data stream into the second FPGA. The clock from the first FPGA is disabled. Each FPGA passes control to the next FPGA in a daisy chain arrangement by enabling the clock source from the next FPGA while disabling the clock source from previous FPGA as each finishes loading its configuration data.

Abstract: An inverter circuit having a readily programmable and stable threshold voltage and low propagation delay. An input stage of the inverter includes a pair of transistors, a first one adapted to receive an input signal for inversion and being disposed in a first current path and a second one being disposed in a second current path. The input stage further comprises a third transistor connected in series with the first transistor and receiving a bias voltage. The first, second, and third transistors are all of the same type; i.e., all NMOS or all PMOS. An output stage of the inverter includes a PMOS transistor and an NMOS transistor having interconnected drain terminals at which an inverted output signal is provided. The threshold voltage about which the output signal transitions is a function of the bias voltage and characteristics of the first, second, and third transistors in the input stage.

Abstract: A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations.

Abstract: A timing generator for generating delay timing signals which have delay time up to n-times of a reference clock period is capable of considerably reducing the hardware size. The timing generator is used in a semiconductor testing apparatus. The timing generator can contribute to reduce the total size and cost of the semiconductor testing apparatus. The timing generator includes a counter for counting the reference clock, an adder for adding the output of the counter to delay data, a series of registers for storing the output of the adder and shifting the output of the adder in synchronism with a delay trigger signal, a series of exclusive OR gates for comparing each output of the registers with the output of the counter and generating coincidence signals when the output from the register and the counter coincide with each other, and an OR gate for receiving the outputs of the exclusive OR gates and generating a signal which is combined of the outputs from the exclusive OR gates.

Abstract: A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.

Abstract: A logic circuit includes a low-threshold logic circuit, a pair of first and second power lines, a first dummy power line, and a first high-frequency logic circuit. The low-threshold logic circuit has a logic circuit element constituted by a plurality of low-threshold field effect transistors. The pair of first and second power lines supply power to the low-threshold logic circuit. The first dummy power line is connected to one of power source terminals of the low-threshold logic circuit. The first high-threshold control transistor is arranged between the first dummy power line and the first power line.

Abstract: A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accomplish this, programming and data input signals that would normally go to the defective logic group are redirected to another logic group. The data output signals of the other group are substituted for the data output signals of the logic group that would normally have received the programming and data input signals that were redirected to the other logic group.

Abstract: A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between conductors are configured using programmable logic. Some of the programmable logic is used to selectively connect logic array block input terminals to the horizontal conductors. Additional logic in each column is used to selectively connect the horizontal conductors to either logic array block output terminals from the same column or logic array block output terminals from an adjacent column. The additional logic prevents certain interconnection pathways from being blocked and increases the overall flexibility of the interconnection scheme of the programmable logic device, thereby improving device performance.

Abstract: An integrated circuit with programmable output drive/program pins includes a plurality of output pads (30) which are each operable to interface with a separate and dedicated output driver (38). The output driver (38) is operable to drive an LED output device (14) in an operating mode. In a program mode, the driver (38) is disabled and a program buffer (40) enabled. At the same time, the LED output device (14) is disabled such that no impedance is presented to the output pad (30) due to operation of the LED output device (14). A programming resistor (18) is disposed between the pad (30) and one of three program reference voltages. A first program state is represented when the resistor (18) is tied to ground, a second program state is represented when the resistor (18) is tied to an open circuit and a third program state is represented when the resistor (18) is tied to a positive voltage.

Abstract: A digital electronic device includes a digital circuit responsive to a logic transition at an input thereof to produce at an output thereof a spurious logic transition ultimately followed by a stable logic level. A transition detector produces a detection signal in response to the logic transition at the digital circuit input, the transition detector including a latch circuit having an output for producing the detection signal. A self-timed circuit receives the detection signal and, after delaying for a suitable time, produces a done signal. A switching circuit is responsive to the done signal to connect the digital circuit output to a selected logic node.

Abstract: A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

Abstract: A source follower circuit which operates at high speed and maintains low power consumption and which includes a pair of small, normally on, NMOS and PMOS transistors and a pair of large, normally off, NMOS and PMOS transistors. The two pairs of transistors are connected in parallel. In each pair of transistors the sources and the gates of the NMOS and PMOS transistors are connected to each other. Furthermore, the threshold voltages of the transistors must be set so that: large NMOS transistor voltage>small PMOS transistor voltage>small NMOS transistor voltage>large PMOS transistor voltage, or so that small PMOS transistor voltage>large NMOS transistor voltage>large PMOS transistor voltage>small NMOS transistor voltage.

Abstract: A low-power, logic signal level converter includes a CMOSFET current mirror differential amplifier with a current control element for providing a level-converted output logic signal in response to an input logic signal while ensuring that virtually no DC current is drawn during steady-state circuit operations. The CMOSFET current mirror differential amplifier includes a PMOSFET current mirror driven by NMOSFET pull-down transistors with a DC current-blocking PMOSFET between them. The interposed PMOSFET blocks DC current flow during steady-state circuit operation without adversely affecting the line driving capacity of the current mirror differential amplifier during logic signal transitions.