Abstract: An emitter-coupled logic circuit includes a differential pair of transistors and an emitter follower output stage. A load inductor is connected to one of the differential transistors and a load resistor is connected to the other one of the differential transistors. The emitter follower output stage having an input node connected to the load resistor and an output node is connected to a constant current source formed by a current source transistor and an inductor which is AC-coupled to the load inductor by a mutual induction effect. The pull-up and pull-down delay times of the emitter coupled logic circuit can be reduced in a wide range from a light load to a heavy load.

Abstract: First and second capacitor circuits responsive to a potential applied to an input node for instantaneously supplying a voltage derived by capacitance division to control electrodes of first and second output MOS transistors which drive an output node. When the output node reaches a predetermined potential level, the control electrode node of the first output transistor or the control electrode node of the second output transistor is driven to ground potential or power supply potential by the MOS transistor responding to a delay signal of an input signal. A smaller buffer circuit which has improved output response and reduced through current is described. The output signal transitioning speed can also be easily altered.

Abstract: A circuit for synchronously selecting either a first or a second input clock signal as an output clock signal includes first and second logic means. The first logic means outputs a first clock signal when an internal control signal is at a first predetermined logic level, while the second logic means outputs a second input clock signal when the internal control signal is at a second predetermined logic level. A control logic means is utilized to select either the first or the second input clock signal as the output of the circuit by coupling the first input clock signal from the first logic means to the output when an input select signal is in a logic state. The second input clock signal is coupled to the output when the input select signal is in a second logic state. The control logic means generates the internal control signal in response to the input select signal.

Abstract: A programmable logic cell array (PLCA) architecture that provides efficient support for demultiplexers or multi-ported register files without sacrificing PLCA functionality or flexibility is disclosed. The architecture of conventional PLCs is modified so that demultiplexers can be implemented in a single PLC operated backwards. Furthermore, read ports and write ports for multi-ported register files can be implemented on a PLCA with individual PLCs serving as either a read port or a write port for a bit slice. In particular, a PLC memory of a PLC is modified such that it can function to pass signals to its inputs from a PLC multiplexer (selector) when the PLC multiplexer (built from a tree of pass transistors) is operated backwards so as to function as a demultiplexer (decoder).

Abstract: The network comprises cells each constituted by a first channel (4, 4') of a material having selectively a superconductive state and a resistive state, refrigeration apparatus to maintain the first channel at a temperature below that which ensures superconductivity of the material below a critical current intensity in the channel, an electrical supply for the channel, and a second channel (5) branched in parallel to the first and having an electrical resistance (R). According to the invention, the two cells are coupled by at least one interconnection channel (8, 9, 10, 11; 8', 9', 10', 11') with unidirectional electrical conduction, extending from the input of one cell to the input of the other cell to input current into this latter or to derive it, a voltage control regulating the intensity of the current flowing from one cell toward the other in the interconnection channel.

Abstract: A data output buffer includes a data driving circuit having a pull-up transistor responsive to a first signal and a pull-down transistor responsive to a second signal, a first control circuit for regulating the slope of the first signal to be less steep after reaching the threshold of the pull-up transistor than before reaching the threshold of the pull-up transistor, and a second control circuit for regulating the slope of the second signal to be less steep after reaching the threshold of the pull-down transistor than before reaching the threshold of the pull-down transistor. As a result, noise generated by the transition of the output signal of the data output buffer is reduced without affecting operation speed.

Abstract: An editing apparatus for use with a tape-form recording medium is provided in which, according to a positioning signal and a tracking pilot signal multiplex-recorded into the first recording area of each track of the recording medium which consists of a plurality of recording areas separated from each other by gaps, a pilot sampling signal for determining the timing of sampling and an editing timing signal for determining the recording location in a desired recording area following the first recording area are produced. After the tracking control is executed through sampling the tracking pilot signals from adjacent tracks at the timing of the pilot sampling signal, a data signal is recorded into the desired recording area after the first recording area according to the editing timing signal.

Abstract: An address buffer (20) provides an ATD pulse in response to an address signal transitioning from one logic state to another. The address buffer (20) includes a differential amplifier (22), an emitter-follower transistor (35), and two P-channel transistors (36 and 37). A first current electrode of each of the P-channel transistors is connected to the output nodes (101 and 102) of the differential amplifier (22), and a second current electrode of each of the P-channel transistors (36 and 37) is connected to the base of the emitter-follower transistor (35). Delayed control signals are provided to the gates of the P-channel transistors (36 and 37) by a level converter circuit (60) to cause an ATD pulse to be provided at the emitter of the emitter-follower transistor (35). Generating the ATD pulse in the address buffer allows the ATD pulse to be produced very quickly.

Abstract: In a method of recording digital signals, in which all audio signals of N channels (N=integer) are recorded on M tracks (M=integer>N) where video signals of I fields (I=integer) are recorded, the improvement including: the M tracks being divided into N track groups each having S tracks (S=integer=M/N) arranged successively such that the audio signals of a j-th channel (j=integer) in the N channels are recorded on the tracks of an i-th track group (i=integer) in the N track groups.

Abstract: A controlled slew rate output buffer has an input stage that generates a charging current in response to the rising edge of an input signal and that generates a discharging current in response to the falling edge of the input signal so that both the charging current and the discharging current are substantially constant over a temperature range and a power supply voltage range. A charging stage responds to the charging current by charging an intermediate node at a first slew rate that is substantially constant over the temperature range and the power supply voltage range. A discharging stage responds to the discharging current by discharging the intermediate node at a second slew rate that is substantially constant over the temperature range and the power supply voltage range.

Abstract: A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data in the data memory circuit, selecting the two input signals supplied to the combinational logic circuit from more than two input signals, a clock-synchronized circuit for supplying the output signal from the combinational logic circuit in synchronization with a clock signal, and a 3-state-output type output select circuit for selecting either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit, depending on the stored data in the data memory circuit.

Abstract: A buffer logic circuit having a lightly doped drain structure, comprising a power source potential, a ground potential, first and second Field Effect Transistors having drain electrodes, gate electrodes supplied with first input signal and a second input signal, respectively, source electrodes being connected to each other, and the drain electrodes for generating output signals corresponding to the input signals, respectively, device, having an end connected to the source electrodes of the first and second FETs, for reducing the potential of the drain electrodes, and device, connected between the other end of the drain electrode potential reducing device and the ground potential, for supplying a constant-current regulated power.

Abstract: A dual mode input buffer having two modes of operation, a first mode of operation which provides a first CMOS level output from a TTL level input while operating at a first voltage level, and a second mode of operation which provides a second CMOS level output from a TTL level input while operating at a second voltage level. A first input provides TTl level inputs. An output provides a first CMOS level output and a second CMOS level output, one at at a time, depending on the mode of operation. A second input selects one of the two operation modes. Buffer means provides buffering of the signals provided on the first input. The buffer means has a level shifting transistor. Trip point level shifting means is provided for maintaining the trip point of the dual mode input buffer at approximately the same voltage level when the dual mode input buffer is operated at the second voltage level as when it operates at the first voltage level. A second input activates said trip point level shifting means.

Abstract: An output driver stage for an integrated circuit device includes slew rate control on the final logic gate. Slew rate control is provided by resistors located in the power supply path for the gate. A switch is connected in parallel across the resistor, and can be used to short the resistor to disable or reduce slew rate limiting. The switch is connected to another location within the output circuitry, and disables or reduces the slew rate limiting resistor during a portion of the switching cycle. This provides for slew rate limiting during a portion of switching when it is most needed, and disables it when slew rate limiting is not required.

Abstract: A voltage interfacing buffer for interfacing a low voltage integrated circuit to a high voltage environment, wherein the integrated circuit contains only low voltage transistors. To drive the high voltage environment at the low voltage swing, the voltage interfacing circuit employs protection circuits and novel n-well biasing of MOS transistors. To drive the high voltage environment at the high voltage swing, the voltage interfacing circuit employs a bias generator circuit to bias buffer transistors supplied with the high voltage. As example applications, the voltage interfacing buffer enables a 3 volt or 3.3 volt integrated circuit chip to drive TTL as well as CMOS voltage levels. Moreover, the voltage interfacing buffer enables a 2 volt integrated circuit chip to drive TTL voltage levels.

Abstract: A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

Abstract: A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the first (30) and the second (32) node and is operable to electrically short-circuit the nodes according to input signals (A.sub.1, A.sub.2, A.sub.3). The screening transistor (Q20) has a first and a second [source-drain region] current electrode and a [gate] control electrode. The first [source-drain region] current electrode is coupled to a third node (34), the second [source-drain region] current electrode is coupled to the second node (32) and the [gate] control electrode is coupled to the first node (30). The clocking circuitry alternately precharges the first (30) and third nodes (34) to a first known voltage level and evaluates the voltage on the first node (30) to output a logic level.

Abstract: An improved helical read/write head is disclosed having a cross-cut groove disposed on the lead sloping surface thereof to improve reliability. The cross-cut groove is positioned between the magnetic gap of the helica head and an initial head/tape interface region of the head and is preferably oriented perpendicular to the longitudinal axis/direction of travel of the tape. The cross-cut groove may be particularly positioned to accommodate and dampen tape disruption attendant to initiating the helical head/tape interface.

Abstract: Disclosed is a slider with an air bearing surface for flying a magnetic transducer on an air lubrication film over a moving recording medium. The air bearing surface allows the slider to fly at a close and substantially uniform height over the disk surface regardless of the skew angle of the air flow. The slider has a pair of nonidentical, nonsymmetrical rails disposed about the longitudinal axis of the slider, which through the viscous effects of the air flow, provide the air lubrication film when the recording medium is in motion.

Abstract: An audio signal of arbitrary length is recorded on a single track of a magnetic disk, and a plurality of corresponding or associated video signals are recorded on successive coaxial tracks. The deviation of each video signal is counted during the reception of the audio signal, and data representative thereof is superposed on the recorded video signals to "coordinate" subsequent playback.