Patents Examined by Benjamin Utech
  • Patent number: 6908292
    Abstract: In the production of a spunbond web by aerodynamically stretching thermoplastic filaments from a spinneret, the stretching nozzle is formed by two nozzle-forming units each of which has a temperature control device, especially a heater, to minimize deformation at the stretching nozzle defining wall. The result is a reduction in the tolerance of the basis weight of the spunbond web.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: June 21, 2005
    Assignee: Reifenhauser GmbH & Co. Maschinenfabrik
    Inventors: Hans Georg Geus, Hans Jürgen Hofemeister, Falk Rösner, Detlef Frey, Karsten Sievers, Udo Schomer
  • Patent number: 6602439
    Abstract: Chemical-mechanical planarization slurries and methods for using the slurries wherein the slurry includes abrasive particles. The abrasive particles have a small particle size, narrow size distribution and a spherical morphology and the particles are substantially unagglomerated.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: August 5, 2003
    Assignee: Superior MicroPowders, LLC
    Inventors: Mark J. Hampden-Smith, Toivo T. Kodas, James Caruso, Daniel J. Skamser, Quint H. Powell
  • Patent number: 6531397
    Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: March 11, 2003
    Assignee: LSI Logic Corporation
    Inventors: Ronald J. Nagahara, Dawn M. Lee
  • Patent number: 6352588
    Abstract: For producing ultra pure materials a first station has a porous gas distributor. A material supply supplies material to the porous gas distributor. A gas source supplies gas to the distributor and through the distributor to the material in contact with the distributor. A heater adjacent the porous gas distributor heats and melts the material as gas is passed through the material. Dopant and a treatment liquid is or solid supplied to the material. Treated material is discharged from the first station into a second station. A second porous gas distributor in the second station distributes gas through the material in the second station. A crucible receives molten material from the second station for casting, crystal growing in the crucible or for refilling other casting or crystal growth crucibles. The material and the porous gas distributor move with respect to each other. One porous gas distributor is cylindrical and is tipped.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: March 5, 2002
    Assignee: Optoscint, Inc.
    Inventor: Kiril A. Pandelisev
  • Patent number: 6284661
    Abstract: A method and an apparatus for cutting a wafer from a crystalline ingot, by directing a stream or streams of etching gas at the crystalline ingot in a vacuum. Waste in cutting can be greatly minimized and the work environment can also be kept clean. Further, excellent surface smoothness can be realized on the cut wafers.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: September 4, 2001
    Assignee: Daido Hoxan Inc.
    Inventors: Takashi Yokoyama, Kazuma Yamamoto, Masato Yamamoto, Takahiro Mishima, Go Matsuda, Shigeki Itou
  • Patent number: 6232232
    Abstract: An organic acid/fluoride-containing solution etchant having high selectivity for BPSG to TEOS. In an exemplary situation, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. The etchant of the present invention may be used to etch desired areas in the BPSG layer, wherein the high selectivity for BPSG to TEOS of etchant would result in the TEOS layer acting as an etch stop. A second etch with a known etchant may be utilized to etch the TEOS layer. The known etchant for the second etch can be less aggressive and, thus, not damage the components underlying the TEOS layer.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: May 15, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Whonchee Lee, Kevin J. Torek
  • Patent number: 6221153
    Abstract: Compressed gases, liquefied gases, or supercritical fluids are utilized as anti-solvents in a crystal growing process for complex molecules. Crystals of the present invention exhibit greater crystal size and improved morphology over crystals obtained by conventional methods.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: April 24, 2001
    Inventors: Trevor Percival Castor, Matthew Albert Britz, Maury David Cosman, Peter Richard d'Entremont, Glenn Thomas Hong
  • Patent number: 6204184
    Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, the insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
  • Patent number: 6203614
    Abstract: A cable assembly for supporting a seed chuck in a crystal puller to grow monocrystalline ingots according to the Czochralski method comprises a cable adapted for generally vertical movement within the crystal puller relative to a source of molten material. A chuck support is connected to an end of the cable within the crystal puller and is configured for supporting the seed chuck. The chuck support is constructed of a refractory material having a high creep rupture strength and comprises an elongate shank having an upper end and a lower end and an enlarged end member at the lower end of the shank. A coupling is constructed of a malleable material and is deformable into engagement with the end of the cable and the upper end of the shank to join the chuck support to the cable.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: March 20, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Carl F. Cherko
  • Patent number: 6200904
    Abstract: The present invention relates to a method of forming a contact hole of a DRAM on the semiconductor wafer. The semiconductor wafer comprises a substrate, a first dielectric layer, two bit lines on the first dielectric layer, a second dielectric layer, and a photo-resist layer comprising an opening to define the pattern of the contact hole. The method comprises performing a first anisotropic etching process to vertically remove a portion of the two dielectric layers and two bit lines to grossly form the contact hole, removing the photo-resist layer in its entirety, performing a thermal oxidation to form a silicon oxide layer on the side walls of the two bit lines, then forming a silicon nitride layer on the surface of the contact hole, and performing a dry etching to remove the silicon nitride layer. There is a silicon oxide layer and a silicon nitride layer between the bit line and the contact hole, and the contact area of the contact hole will not be reduced.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: March 13, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Wayne Tan, Gwo-Shii Yang, Kun-Chi Lin
  • Patent number: 6184145
    Abstract: In a method of manufacturing a semiconductor device, a laminate film is formed on an insulating film which is formed on a semiconductor substrate. The laminate film is composed of a conductive layer and an insulating layer formed on the conductive layer. A first etching process is carried out to the laminate film using a first mask to form a first group of patterns for first gates and a second group of patterns. Then, a polysilicon layer for pad polysilicon films is deposited after the first etching process. Subsequently, a second etching process is carried out to the patterns of the second group using a second mask to form a third group of patterns for second gates.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: February 6, 2001
    Assignee: NEC Corporation
    Inventor: Yoshihiro Takaishi
  • Patent number: 6179909
    Abstract: In the work crystal orientation adjusting method, the crystal orientations of a work 22 in the rotational direction and in the horizontal direction thereof are measured by an orientation measuring device 76. In accordance with the measured value of the crystal orientation of the work 22 in the rotational direction, the work 22 is rotated about the axis thereof to thereby adjust the crystal orientation of the work 22 in the rotational direction. On the outer surface of the work 22, there are put marks M1 and M2 indicating reference positions for adhesion of an auxiliary plate B which is used to cut the work 22. The auxiliary plate B is adhered to the outer peripheral surface of the work 22 based on the marks M1 and M2. A work mounting plate 53 is mounted onto a support base 40 to thereby support the work 22 on the support base 40.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: January 30, 2001
    Assignees: Nippei Toyama Corporation, Sumitomo Sitix Corporation
    Inventors: Yoshiaki Banzawa, Kazunori Onizaki
  • Patent number: 6176978
    Abstract: The present invention provides a method of reducing particles within a deposition chamber without affecting bias voltage repeatability in subsequently processed wafers. Particularly, it has been discovered that within a high density plasma deposition chamber, the first wafer processed following deposition of a pasting layer may exhibit inconsistent quality as compared to subsequently processed wafers. It has further been discovered that such altered quality arises due to inconsistent bias voltage coupling between a wafer support and a wafer positioned thereon. To maintain consistent bias voltage coupling a transitional layer is deposited within the deposition chamber as part of the pasting process. It is believed the transitional layer affects the chamber's environment (chamber surfaces and atmosphere) which in turn affects bias voltage coupling between the wafer support and a wafer positioned thereon. Preferably the transitional layer is the same layer deposited on production wafers.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: January 23, 2001
    Assignee: Applied Materials, Inc.
    Inventor: Kenny King-tai Ngan
  • Patent number: 6171967
    Abstract: A metal wire forming method for a semiconductor device includes the step of forming a first insulator film over a substrate having at least a second insulator film formed thereon and a first conductive layer formed on the second insulator film. Next, a photosensitive film is formed on the first insulator film, and the photosensitive film is exposed and developed according to a contact hole pattern. This exposes a portion of the first insulator film, and the exposed portion is then etched using the photosensitive film as a mask to form a contact hole in the first insulator film. The method further includes the steps of exposing and developing the photosensitive film according to a trench pattern which includes the contact hole pattern, and etching the first insulator film using the photosensitive film as the mask so that a trench having a predetermined depth is formed in the first insulator film and the first conductive layer is exposed via the contact hole.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: January 9, 2001
    Assignee: LG Semicon Co., Ltd.
    Inventor: Young-Kwon Jun
  • Patent number: 6156659
    Abstract: An apparatus for closed loop slurry distribution during semiconductor wafer polishing operations. The traditional peristaltic pump for slurry supply is eliminated thus eliminating irregularities in the conventional slurry supply. Common platform mounting of the slurry reservoir and the polishing apparatus resulting in concurrent and identical motion of the slurry supply reservoir and the polishing apparatus. The polishing medium is mounted on the outside of a cylinder as opposed to the conventional table mounting, the polishing medium rotates around the axis of the cylinder on which this polishing medium is mounted. The polishing pads are in direct physical contact with the slurry supply without the intervention of any slurry pumping arrangement.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: December 5, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Sudipto Ranendra Roy
  • Patent number: 6156665
    Abstract: The specification describes a trilevel resist technique for defining metallization patterns by lift-off. The trilevel resist comprises two standard photoresist levels separated by a thin silicon oxide layer with approximate composition SiO.sub.2.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: December 5, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan
  • Patent number: 6153534
    Abstract: A dual material gate is effectively fabricated for a field effect transistor having a short channel length of submicron and nanometer dimensions such that disadvantageous short channel effects are minimized. Generally, the method of the present invention includes a step of forming a first material gate portion on a gate dielectric. The first material gate portion has a source side and a drain side, and an aspect of the present invention further includes the step of depositing a spacer dielectric layer on the source side and the drain side of the first material gate portion. An aspect of the present invention also includes the step of implanting heavy ions into the spacer dielectric layer at an angle such that the spacer dielectric layer at the drain side of the first material gate portion is substantially not implanted with the heavy ions. The spacer dielectric layer is then selectively etched such that any portion of the spacer dielectric layer that is implanted with the heavy ions is etched.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: November 28, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei Long, Qi Xiang, Yowjuang W. Liu
  • Patent number: 6143070
    Abstract: The present invention describes the growth of single crystals of non-congruently melting alloys, in particular, silicon-germanium of constant composition in a quartz ampoule by the use of CaCl.sub.2 as an encapsulant for the liquid encapsulated zone melting (LEZM) technique. The zone melting process was modified with the addition of calcium chloride which acts as a liquid encapsulant at temperatures above 660.degree. C. so that the crystal can grow without sticking to the container. The calcium chloride encapsulant creates a non-wetting buffer layer between the quartz container and the SiGe charge material allowing single crystal growth of mixed alloys. The crystal growth system consists of a vertical tube RF furnace with a water cooled split-ring concentrator. The concentrator is 5 mm. Thick by 25 mm diameter and provides a high temperature melt zone with a "spike" profile.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: November 7, 2000
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: David F. Bliss, Brian G. Demczyk, John Bailey
  • Patent number: 6139903
    Abstract: A method of controlling and operating a fluid dispensing apparatus is provided which modifies a tool speed signal from a robot and generates a corrected signal to a dispenser nozzle flow controller to compensate for non-linear flow characteristics of fluids, such as non-Newtonian adhesive fluids, to maintain uniform bead size as the tool speed varies. The corrected tool speed signal is generated by computing the ideal flow for the tool speed, comparing the computed flow with actual flow data stored in memory using linear interpolation of data between the stored values, and generating a control signal modified in accordance with the comparison. The stored data is acquired by operation of the apparatus in a calibration mode wherein a series of standard signals is sent to the fluid controller while the actual flow at each signal level is measured and stored in a table. The method corrects for non-linear flow phenomena such as that known as the shear-thinning effect that is flow rate dependent.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: October 31, 2000
    Assignee: Nordson Corporation
    Inventors: Carl N. Baron, Stephen L. Merkel, Robert C. Hall
  • Patent number: 6110534
    Abstract: A method and an apparatus for modifying a surface layer formed on the surface of a base material in order to modify the characteristics of the surface layer such as to control the chemical composition of the surface layer and to develop a novel utilization of ultra-pure water.The method includes the step of contacting a surface layer on a base material with ultra-pure water in an oxygen-free atmosphere. The amount of dissolved oxygen in the water is preferably 1 ppm or below, and the ultra-pure water is preferably boiled.The apparatus includes a chamber having inert gas introduction means for introducing an inert gas thereinto, and inert gas discharge means for discharging the inert gas therefrom, a container disposed inside the chamber for holding ultra-pure water, and heating means disposed in the chamber for heating ultra-pure water held in the ultra-pure water container.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: August 29, 2000
    Assignee: Tadahiro Ohmi
    Inventors: Tadahiro Ohmi, Yoshinori Nakagawa