Patents Examined by Benjamin Utech
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Patent number: 6022810Abstract: An interconnection layer 3 in a floating state and an interlayer insulating film 6 are formed on a semiconductor substrate. A connection hole 4 penetrating the interlayer insulating film and the interconnection layer is formed by dry etching with fluorocarbon. Filled in the connection hole is a conductive member 5 which is electrically connected to the interconnection layer. Accordingly, an improved method for manufacturing a semiconductor device offering a reduced contact resistance even for an extremely small contact hole is obtained.Type: GrantFiled: April 10, 1998Date of Patent: February 8, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshihiro Kusumi, Takahiro Yokoi, Satoshi Iida
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Patent number: 6020269Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon nitride layer over the oxide layer; depositing an ultra-thin photoresist over the silicon nitride layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon nitride layer; etching the exposed portion of the silicon nitride layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: February 1, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6020262Abstract: Areas of different temperatures are provided on a semiconductor wafer to improve uniformity in polishing rates during CMP.Type: GrantFiled: March 6, 1998Date of Patent: February 1, 2000Assignees: Siemens Aktiengesellschaft, International Business Machines Corp.Inventors: Michael Lester Wise, Jeremy Kaspar Stephens, Suri G. Hedge
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Patent number: 6020267Abstract: A method for fabricating local interconnect metal structures, overlying metal filled via hole openings, has been developed. This invention features the creation of an aluminum based interconnect structure, comprised with an underlying titanium nitride layer. The titanium nitride layer overlays a metal filled via hole, during a photolithographic exposure that is used for formation of the photoresist shapes that are needed for local interconnect metal structure patterning. The anti-reflective properties of the titanium nitride layer allow the formation of the resulting photoresist shapes to be defined without interfering reflections from the underlying metal plug.Type: GrantFiled: March 16, 1998Date of Patent: February 1, 2000Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhon-Jhy Liaw, Ching-Yau Yang
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Patent number: 6020271Abstract: A refractory metal layer is formed on the entire surface of an interlayer insulating film having a connection hole, and then etched back by using an etching gas containing at least one of Kr, Xe, and Rn, each of which is an inert gas element having a large atomic weight. A contact plug is formed by using a resulting refractory metal layer. By employing this manufacturing method, a refractory metal layer formed by the blanket CVD method can be etched while the loading effect is prevented during overetching, and a contact plug having a flat burying surface can be formed without causing any abnormal eroded portion in a connection hole of an interlayer insulating film.Type: GrantFiled: February 3, 1998Date of Patent: February 1, 2000Assignee: Sony CorporationInventor: Toshiharu Yanagida
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Patent number: 6019839Abstract: A method and apparatus for forming an epitaxial titanium silicide film is described. According to the present invention, a monocrystalline silicon substrate is placed in a deposition chamber and heated to a temperature between 710-770.degree. C. A silicon source gas and titanium tetrachloride are then provided into the deposition chamber. The deposition pressure is maintained between 5-10 torr. An epitaxial titanium silicide film is then formed on the substrate from the silicon source gas and the titanium tetrachloride.Type: GrantFiled: April 17, 1998Date of Patent: February 1, 2000Assignee: Applied Materials, Inc.Inventors: Vedapuram S. Achutharaman, Johanes Swenberg
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Patent number: 6017824Abstract: A process of opening, a stack of large diameter via holes, in a multiple levels of insulator layers, to be used for access of a laser repair procedure, applied to underlying integrated circuit shapes, while simultaneously opening small diameter via holes, in the same multiple levels of insulator layers, to be used to accommodate metal plug structures, has been developed. The process features the use of a polysilicon stop layer, used at the bottom of the stack of large diameter via holes, protecting underlying components of the underlying integrated circuit, from the dry and wet etching procedures used for the creation of the stack of large diameter via holes. The process also features the formation of metal spacers, on the sides of the large diameter via holes, created simultaneously during the formation of metal plug structures, and used again to protect the multiple levels of insulator layer, that would have been exposed, if left unprotected, during a wet etching procedure.Type: GrantFiled: November 16, 1998Date of Patent: January 25, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Hua Lee, James Wu
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Patent number: 6017821Abstract: A method for forming plugs using chemical-mechanical polishing, which includes providing a conductive layer having an inter-layer dielectric formed thereon; then, forming a contact hole in the inter-layer dielectric exposing portions of the conductive layer. Thereafter, a diffusion barrier layer and a glue layer are sequentially formed over the inter-layer dielectric and the exposed conductive layer. Next, a first metallic layer is deposited over the glue layer, and then etched back to form a residual first metallic layer. Subsequently, a second metallic layer is deposited over the glue layer and the residual first metallic layer. Finally, chemical-mechanical polishing is used to remove the second metallic layer above the inter-layer dielectric to form a metal plug. By depositing plug metal in stages, exposed cavities are no longer formed after a CMP operation is performed, thus avoiding the problem of CMP slurry getting inside a metal plug.Type: GrantFiled: October 28, 1997Date of Patent: January 25, 2000Assignee: Winbond Electronics Corp.Inventors: Sen-Shan Yang, Jye-Yen Cheng
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Patent number: 6015754Abstract: A CMP apparatus is used to subject a target surface of a semiconductor wafer to a polishing treatment, by moving the target surface and a polishing surface of a polishing cloth relative to each other while supplying a polishing liquid between the target surface and the polishing surface. Electric resistance is measured between pairs of measuring points arranged on opposite sides of dicing lines on the target surface, while subjecting the target surface to the polishing treatment. The polishing treatment is caused to be ended by comparing detected values of a changing rate in measured values of the electric property with a reference value set to correspond to an end point of the polishing treatment.Type: GrantFiled: December 23, 1997Date of Patent: January 18, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Yasukazu Mase, Yoshitaka Matsui, Takeshi Kubota, Toshihiko Kitamura
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Patent number: 6013134Abstract: An apparatus for forming a portion of an electronic device is described incorporating an Ultra High Vacuum-Chemical Vapor Deposition (UHV-CVD) system, a Low Pressure-Chemical Vapor Deposition (LP-CVD) system, and an Ultra High Vacuum (UHV) transfer system. A method for passivating a semiconductor substrate is described incorporating growing silicon containing layers, flowing a hydrogen containing gas and lowering the substrate temperature below 400.degree. C. A method for removing native oxide is described. A method for growing a continuous epitaxial layer while performing a deposition interrupt is described. A method for forming a Si/Si oxide interface is described having low interface trap density. A method for forming a Si/Si oxide/p++ polysilicon gate stack. The invention overcomes the problem of requiring silicon containing wafers being dipped in HF acid prior to CVD processing. The invention overcomes the problem of surface passivation between in-situ processes in multiple CVD reactors.Type: GrantFiled: February 18, 1998Date of Patent: January 11, 2000Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid Ezzeldin Ismail
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Patent number: 6013534Abstract: A method of thinning integrated circuits in die form including acquiring a handle wafer; depositing an etch stop material on the handle wafer; coating an adhesive layer onto the etch stop material; acquiring a template wafer; cutting an opening through the template wafer; placing dice onto the adhesive layer of the handle wafer; bonding the template wafer onto the handle wafer; filling any gaps with adhesive material; thinning the resulting structure; acquiring a transfer wafer; coating an adhesive layer onto the transfer wafer; bonding the transfer wafer to the resulting structure; removing the handle wafer; removing the etch stop material; removing any remaining adhesive material; testing electrically the thinned dice; recording which of the thinned dice are functional; dicing the transfer wafer into portions; holding temporarily the portions; removing the transfer wafer from the portions; and packaging the thinned dice.Type: GrantFiled: July 25, 1997Date of Patent: January 11, 2000Assignee: The United States of America as represented by the National Security AgencyInventor: David Jerome Mountain
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Patent number: 6013130Abstract: Layers of compound semiconductor 60 are grown epitaxially on a substrate 40. One or more components 24 are removed from a target 14 by a supply of energy 18, and reacted with gas surrounding the target. The gas stream conveys the components through a nozzle 34 to achieve a uniform layer on the substrate.Type: GrantFiled: March 22, 1996Date of Patent: January 11, 2000Assignee: Deutsche Forschungsanstalt Fuer Luft- und Raumfahrt e.V.Inventors: Ralph Dieter, Hans Opower, Heinrich Weyer
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Patent number: 6010965Abstract: Aluminum extrusions in overlying vias are prevented by depositing the underlying aluminum layer at a high temperature, preferably at a temperature greater than any temperature to which the wafer is exposed during subsequent processing. Embodiments include sputter depositing the underlying aluminum layer at a temperature of about 430.degree. C. to about 570.degree. C.Type: GrantFiled: December 18, 1997Date of Patent: January 4, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Jeffrey A. Shields
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Patent number: 6010968Abstract: A multilevel contact etching method to form a contact opening is provided. The method contains using an inductively coupled plasma (ICP) etcher to produce a high plasma density condition. The plasma gas etchant is composed of C.sub.4 F.sub.8 /CH.sub.2 F.sub.2 /CO/Ar with a ratio of 3:4:12:80 so that silicon nitride can be selectively etched while the silicon and silicide are not etched. Each content ratio of the plasma gas etchant allows a variance of about 20%. Wall temperature of the ICP etcher is about 100.degree. C.-300.degree. C. A cooling system for a wafer pad is about -20.degree. C.-20.degree. C. Chamber pressure is about 5-100 mtorr. Bias power on the wafer pad is about 1000 W-3000 W. Source power of an inductance coil is about 500 W-3000 W.Type: GrantFiled: December 24, 1998Date of Patent: January 4, 2000Assignee: United Microelectronics Corp.Inventors: Chan-Lon Yang, Tong-Yu Chen, Keh-Ching Huang
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Patent number: 6007623Abstract: A method for producing a horizontal magnetic recording medium that has as its magnetic film a granular film with grains of a chemically-ordered FePt or FePtX (or CoPt or CoPtX) alloy in the tetragonal L1.sub.0 structure uses an etched seed layer beneath the granular film. The granular magnetic film reveals a very high magnetocrystalline anisotropy within the individual grains. The film is produced by sputtering from a single alloy target or cosputtering from several targets. The granular structure and the chemical ordering are controlled by means of sputter parameters, e.g., temperature and deposition rate, and by the use of the etched seed layer that provides a structure for the subsequently sputter-deposited granular magnetic film. The structure of the seed layer is obtained by sputter etching, plasma etching, ion irradiation, or laser irradiation. The magnetic properties, i.e., H.sub.c and areal moment density M.sub.Type: GrantFiled: August 29, 1997Date of Patent: December 28, 1999Assignee: International Business Machines CorporationInventors: Jan-Ulrich Thiele, Dieter Klaus Weller
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Patent number: 6006764Abstract: The present invention provides a method of removing photoresist from a wafer surface having a bonding pad using a three step clean composed of (1) a wet cleaning the substrate, (2) a F-containing gas high temperature plasma treatment which prevents the corrosion of aluminum contact pad, and (3) completely striping the photoresist strip using an O.sub.2 dry ash. The invention eliminates metal bonding pad corrosion and the completely removes residual photoresist from keyholes.Type: GrantFiled: January 28, 1997Date of Patent: December 28, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Tao Chu, Ching-Wen Cho, Chia-Hung Lai, Chih-Chien Hung
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Patent number: 6007732Abstract: A pattern forming method having a step of forming an amorphous carbon film on a patterning layer formed on a substrate, a step of forming a photoresist film on the amorphous carbon film, a step of selectively exposing and developing the photoresist film to form a photoresist pattern, and a step of successively dry-etching the amorphous carbon film and the patterning layer by using the photoresist film as an etching mask. Desired optical constants of an amorphous carbon film formed by sputtering can be obtained by controlling a substrate temperature and other parameters.Type: GrantFiled: May 5, 1997Date of Patent: December 28, 1999Assignee: Fujitsu LimitedInventors: Koichi Hashimoto, Toshiyuki Ohtsuka, Fumihiko Shinpuku, Daisuke Matsunaga, Takayuki Enda
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Patent number: 6008127Abstract: A process for fabricating a semiconductor device using an etching stopper film which does not increase the number of photo-etching steps and does not cause a deterioration in device characteristics comprises the steps of: forming an impurity region at the surface of a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a first hole in the first insulating layer and thereby exposing the impurity region; forming a first metal layer on the first insulating layer and the inner surface of the first hole; forming a second metal layer on the region of the first metal layer formed on the inner surface of the first hole and filling the first hole with the second metal layer; oxidizing the first metal layer with the second metal layer as a mask; forming a second insulating layer on the first metal layer and the second metal layer; forming a second hole in the second insulating layer exposing the second metal layer by etching the second insulating layer with the first metalType: GrantFiled: November 7, 1997Date of Patent: December 28, 1999Assignee: Kabushiki Kaisha ToshibaInventor: Masaki Yamada
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Patent number: 6008140Abstract: Copper can be pattern etched in a manner which provides the desired feature dimension and integrity, at acceptable rates, and with selectivity over adjacent materials. To provide for feature integrity, the portion of the copper feature surface which has been etched to the desired dimensions and shape must be protected during the etching of adjacent feature surfaces. To avoid the trapping of reactive species interior of the etched copper surface, hydrogen is applied to that surface. Hydrogen is adsorbed on the copper exterior surface and may be absorbed into the exterior surface of the copper, so that it is available to react with species which would otherwise penetrate that exterior surface and react with the copper interior to that surface. Sufficient hydrogen must be applied to the exterior surface of the etched portion of the copper feature to prevent incident reactive species present due to etching of adjacent feature surfaces from penetrating the previously etched feature exterior surface.Type: GrantFiled: August 13, 1997Date of Patent: December 28, 1999Assignee: Applied Materials, Inc.Inventors: Yan Ye, Allen Zhao, Xiancan Deng, Diana Xiaobing Ma
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Patent number: 6007873Abstract: A high emissivity coating composition for coating the interior of a furnace to direct thermal energy toward a load in the furnace wherein the furnace operates above 1100.degree. C. thereby increasing the thermal efficiency of the furnace. The high emissivity coating composition includes a high emissivity agent and a binder agent. The preferred high emissivity agent is cerium oxide which defines a high emissivity factor from approximately 1000.degree. C. to above 2000.degree. C. The binder suspension agent is formulated to define the consistency and drying characteristics of paint such that the coating can be applied in a manner similar to the manner in which paint is applied. Moreover, the binder/suspension agent withstands the final use temperature.Type: GrantFiled: April 28, 1997Date of Patent: December 28, 1999Assignee: Equity EnterprisesInventors: Cressie E. Holcombe, Jr., Lloyd R. Chapman