Patents Examined by Benjamin Utech
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Patent number: 6043159Abstract: Process for the chemical mechanical polishing of a layer of isolating material based on silicon or a silicon derivative, in which abrasion of the layer of isolating material is carried out by rubbing said layer using a fabric which brings into play an abrasive containing an acid aqueous solution of colloidal silica containing individualized colloidal silica particles, not linked together by siloxane bonds, and water as the suspension medium and new abrasives based on such suspensions.Type: GrantFiled: September 30, 1997Date of Patent: March 28, 2000Assignee: Clariant Chimie S.A.Inventors: Eric Jacquinot, Maurice Rivoire
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Patent number: 6040246Abstract: To form an integrated optical component comprising a thick waveguide coupled to a thin waveguide, the method consists in:depositing a first guiding layer of said thick waveguide on a substrate;locally etching said first guiding layer over a portion allocated both to a coupling interface and to the thin waveguide;depositing a second guiding layer on the first guiding layer and on the locally etched portion so as to form said thick waveguide in a manner such that it has a maximum thickness in a first zone, a graded-thickness section in a second zone, and a reduced-thickness section in a third zone;locally etching the second guiding layer over a portion of the third zone, said portion being allocated to the thin waveguide; anddepositing a third guiding layer in said portion of said third zone so as to form said thin waveguide.Type: GrantFiled: September 8, 1998Date of Patent: March 21, 2000Assignee: AlcatelInventors: Leon Goldstein, Denis Leclerc, Beatrice Dagens
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Patent number: 6040247Abstract: A method for etching a contact for forming a contact hole having a sidewall profile with a single process by controlling a flow rate of carrier gas at an etcher having a mixture of gases, the mixture including CF.sub.4, a polymer forming gas and a carrier gas, including steps for forming an insulation layer on a substrate, exposing a portion of the insulation layer by providing a photoresist pattern on the insulation layer, etching the insulation layer to form the contact hole, the contact hole having a sloped sidewall. The step of etching the insulation layer includes the steps of, introducing a plurality of gases into an etching chamber, the plurality of gases including a first gas including CF.sub.4, a second gas including a polymer forming gas, and a third gas including a balance gas and controlling a flow rate into the etching chamber of the balance gas, and removing the photoresist pattern from the insulation layer.Type: GrantFiled: January 7, 1997Date of Patent: March 21, 2000Assignee: LG Semicon Co., Ltd.Inventor: Seong Woo Chung
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Patent number: 6037264Abstract: A method of etching a platinum electrode layer disposed on a substrate. The method comprises providing a substrate supporting a platinum electrode layer, an insulation layer on the platinum electrode layer, and a resist layer on the insulation layer. A portion of the insulation layer is etched by employing a plasma of an etchant gas to break through and to remove the portion of the insulation layer from the platinum electrode layer to expose part of the platinum electrode layer. The exposed part of the platinum electrode layer is then etched by employing a plasma of an etchant gas comprising argon. The etched platinum electrode layer is subsequently overetched by employing a high density plasma of an etchant gas to remove redeposited veils from the etched platinum electrode layer. The etched platinum electrode layer is employed in a semiconductor device.Type: GrantFiled: August 10, 1999Date of Patent: March 14, 2000Assignee: Applied Materials, Inc.Inventor: Jeng H. Hwang
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Patent number: 6037261Abstract: A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer.Type: GrantFiled: February 23, 1998Date of Patent: March 14, 2000Assignee: Micron Technology, Inc.Inventors: Mark E. Jost, Phillip G. Wald
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Patent number: 6033987Abstract: A method for chemically-and-mechanically polishing a semiconductor wafer surface is disclosed. It includes the steps of: (a) providing a mechanical polishing pad; (b) placing a pressure-sensitive film on top of a wafer surface to be polished by the mechanical polishing pad, the pressure-sensitive film contains materials that will show pressure-dependent colors when subject to an external pressure; (c) commencing a chemically-and-mechanically polishing process so that the mechanical polishing pad exerts a pressure on the pressure-sensitive film; (d) scanning the pressure-dependent color pattern on the pressure-sensitive film; (e) converting the pressure-dependent color pattern into a pressure distribution; and (f) adjusting the mechanical polishing pad, or a leveling of the wafer mounting, or both, according to the pressure distribution obtained in step (e).Type: GrantFiled: January 15, 1999Date of Patent: March 7, 2000Assignee: Winbond Electronics Corp.Inventors: Chi-Fa Lin, Wen-Tsu Tseng, Min-Shinn Feng
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Patent number: 6033993Abstract: A process of treating a substrate having photoresist applied thereto, comprising the steps of:(a) removing said photoresist from said substrate by a method selected from the group consisting of photoresist stripping, plasma etch residue cleaning, or a combination thereof; and(b) rinsing said substrate with a non-corrosive rinsing composition comprising(1) water; and(2) one or more water-soluble corrosion inhibitors selected from the group consisting essentially of hydroxylamine, at least one hydroxylammonium salt, at least one water-soluble organic acid, at least one amino acid, and combinations thereof.Type: GrantFiled: September 23, 1997Date of Patent: March 7, 2000Assignee: Olin Microelectronic Chemicals, Inc.Inventors: M. Lee Love, Jr., Kenji Honda
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Patent number: 6032682Abstract: The present invention provides methods for efficiently cleaning semiconductor wafers, and particularly for removing photoresist material from the surfaces of semiconductor wafers, using a mixture of sulfuric acid and hydrogen peroxide. In accordance with the present invention, an initial sulfuric acid-based photoresist stripping bath, either being pure sulfuric acid or a sulfuric acid:hydrogen peroxide mixture with a ratio of at least 15:0.3, based on the anhydrous chemical substances, is prepared for processing an initial batch of wafers. During the processing of the semiconductor wafers, hydrogen peroxide is added to the bath solution at a controlled rate of between about 0.015-1.5 g H.sub.2 O.sub.2 (anhydrous basis)/min./liter of photoresist bath solution. In such a way, the conversion of hydrogen peroxide to Caro's acid is optimized resulting in an extended bath life and conservation of hydrogen peroxide.Type: GrantFiled: June 24, 1997Date of Patent: March 7, 2000Assignee: CFMT, IncInventor: Steven Verhaverbeke
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Patent number: 6030897Abstract: An alignment mark is formed in a planar semiconductor IC structure coated by a layer opaque to the radiations of the photo-stepper used to perform a photolithographic step. First, there is provided a structure comprised of a silicon substrate (11) having at least one shallow isolation trench (17A) in the chip region (13) and one shallow alignment trench (17B') in the kerf region (14) of the substrate wherein said alignment trench has a determined width (W'). Then, a layer (18) of an insulating material is conformally deposited onto the structure. Its thickness is adequate to over fill the trenches so that depressions (18A, 18B') are created above the locations of said isolation and alignment trenches. Next, the structure is planarized by filling the depression over said isolation trench but not the depression (18B') formed over said alignment trench to preserve it.Type: GrantFiled: May 28, 1998Date of Patent: February 29, 2000Assignee: International Business Machines CorporationInventor: Pascal Deconinck
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Patent number: 6031654Abstract: A low magnetic saturation type bismuth-substituted rare-earth iron garnet crystal film of the invention is grown on a substrate of (111) garnet single crystal (GdCa)3(GaMgZr)5O12 by using a liquid phase epitaxial method. This single crystal has a lattice constant of 1.2497.+-.0.0002 nm and has a chemical structural formula expressed byTb.sub.3-x Bi.sub.x Fe.sub.5-y-z Ga.sub.y Al.sub.z O.sub.12wherein x has the range 1.25<.times.<1.40, y+z has the range 0.50<y+z<0.65, and z/y has the range 0.45<z/y<0.75.Type: GrantFiled: May 21, 1998Date of Patent: February 29, 2000Assignee: Mitsubishi Gas Chemical Company, Inc.Inventors: Kiyonari Hiramatsu, Kazushi Shirai, Norio Takeda
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Patent number: 6030425Abstract: A slurry for chemical-mechanical polishing comprises a high pH solution with particles of a catalyst mixed with the high pH solution for accelerating the polishing rate. The catalyst preferably is a metal selected from the group consisting of platinum, silver, palladium, copper, rhodium, nickel, and iron. The catalyst may be impregnated into a polishing pad used to apply the slurry to a surface. A CMP process for metal surfaces includes applying a slurry to a metal surface to be polished, and providing an electrical bias to the workpiece and to the slurry for controlling the polishing rate. The electrical bias is provided to dies in the workpiece by means of an electrical connection between a bias voltage source and scribe lines between adjacent dies.Type: GrantFiled: April 27, 1999Date of Patent: February 29, 2000Assignee: LSI Logic CorporationInventor: William Y. Hata
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Patent number: 6030903Abstract: A method for non-destructively determining the amount of undercutting in a hidden layer of material disposed on a substrate after device patterning by etching. The method involves forming at least two lines of etch resistant material of increasing width over the hidden layer of material of the substrate and inspecting the lines after etching for a given time period to determine how many lines have been removed. The width dimension of the largest removed line corresponds approximately to the amount of undercut for two sides in the hidden layer of material after etching for the given time period.Type: GrantFiled: November 5, 1998Date of Patent: February 29, 2000Assignee: Lucent Technologies Inc.Inventor: Kenneth Gerard Glogovsky
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Patent number: 6027660Abstract: A method of patterning a ceramic slider by plasma etching is disclosed. The ceramic slider contains alumina and titanium carbide. The method includes the steps of forming an etch pattern by depositing and developing a photoresist on the ceramic slider, and reactive ion etching a first surface on the ceramic slider using an etchant gas. The etchant gas generally includes argon, and a fluorine containing gas. The power source density, during etching ranges from about 0.5 W/(cm.sup.2) to 8 W/(cm.sup.2). Another aspect of the invention is a ceramic slider resulting from the method of the invention having a smoothness ranging from about 20 to 300 .ANG. as measured by atomic force microscopy.Type: GrantFiled: May 11, 1998Date of Patent: February 22, 2000Assignee: International Business Machines CorproationInventors: Richard Hsiao, Cherngye Hwang, Son Van Nguyen, Diana Perez
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Patent number: 6027565Abstract: An apparatus for producing crystals of a macromolecule in microgravity includes a container 100 which is made of a material having a low thermal conductivity and an open end. A thermally conductive lid 102 is fitted on the open end of the container to close the container and a heat source/sink 114 is provided in thermal contact with the thermally conductive lid to generate a temperature gradient within the container. When a solution of the macromolecule is provided in the container, the temperature gradient induces and control the crystallization of the macromolecule. In operation, a temperature ramp from a start temperature to an end temperature is used to maintain and control the temperature gradient.Type: GrantFiled: October 9, 1997Date of Patent: February 22, 2000Inventors: Charles E. Bugg, Lawrence L. Delucas, Tattanhalli L. Nagabhushan, Paul P. Trotta, Michael D. Harrington, John Bradford Bishop, deceased, by Sue C. Bishop, executrix
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Patent number: 6025278Abstract: In one aspect, the invention includes a method for manufacturing a semiconductive wafer comprising: a) providing a semiconductive material wafer having a front surface and a back surface; b) contacting the front surface with a first fluid; c) contacting the back surface with a second fluid different than the first fluid, at least one of the first and second fluids being configured to etch the semiconductive material of the wafer; at least one of the first and second fluids having a measurable component at a first concentration which is different than any concentration of said measurable component in the other of the first and second fluids; d) etching the semiconductive wafer with the at least one of the first and second fluids configured to etch the semiconductive material; and e) monitoring the measurable component concentration in at least one of the first fluid or the second fluid to ascertain if the etching has formed an opening extending completely through the substrate.Type: GrantFiled: August 22, 1997Date of Patent: February 15, 2000Assignee: Micron Technology, Inc.Inventor: J. Brett Rolfson
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Patent number: 6025272Abstract: A method of manufacturing a semiconductor device including a step of filling crevices or non-level regions formed during the manufacture of the semiconductor device with a spin-on dielectric material. The spin-on dielectric material prevents conductive material from filling the crevices and causing the device to fail.Type: GrantFiled: September 28, 1998Date of Patent: February 15, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Allen S. Yu, Thomas C. Scholer, Paul J. Steffan
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Patent number: 6022808Abstract: Copper interconnects with enhanced electromigration are formed by filling a via/contact hole and/or trench in a dielectric layer with undoped Cu. A Cu layer containing a dopant element, such as Pd, Zr or Sn is deposited on the undoped Cu contact/via and/or line. Annealing is then conducted to diffuse the dopant element into the copper contact/via and/or line to improve its electromigration resistance. CMP is then performed.Type: GrantFiled: March 16, 1998Date of Patent: February 8, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Takeshi Nogami, Shekhar Pramanick, Dirk Brown
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Patent number: 6022485Abstract: A catalytic method and an apparatus for selectively removing material from a solid substrate is provided. The method comprises contacting a surface of a solid substrate with a catalyst material in the presence of a reactant under conditions effective to selectively remove material from those areas of said solid substrate in contact with said catalyst material and said reactant.Type: GrantFiled: October 17, 1997Date of Patent: February 8, 2000Assignee: International Business Machines CorporationInventor: Roger W. Cheek
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Patent number: 6022751Abstract: A process for producing an electronic device having a silicon nitride film on a substrate is provided which comprises steps of forming a silicon nitride film and a silicon oxide film on a first face and a second face reverse to the first face of the substrate respectively, removing the silicon oxide film on the first face by wet etching, removing the silicon nitride film on the first face by wet etching, and removing the silicon oxide film on the second face by wet etching.Type: GrantFiled: October 22, 1997Date of Patent: February 8, 2000Assignee: Canon Kabushiki KaishaInventors: Hitoshi Shindo, Akira Okita
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Patent number: 6022809Abstract: A composite shadow ring for use in an etch chamber that does not generate contaminating oxygen gas when bombarded by a gas plasma and a method for using such composite shadow ring are presented. The composite shadow ring may have a structure of a body portion of a ring shape that is made of a material that is substantially of silicon dioxide and an insert portion which is intimately joined to the body portion and is adjacent to a plasma cloud in the etch chamber when the shadow ring is positioned juxtaposed to the wafer, the insert portion of the shadow ring may also have a ring shape and is eccentric with the body portion, it generally has a diameter smaller than a diameter of the body portion, the insert portion may be fabricated of a material that does not generate oxygen when bombarded by a fluorine-containing gas plasma. The body portion may have a crosssection of a rectangle which has an upper inner corner of the rectangle missing to form a cavity for receiving an insert member intimately therein.Type: GrantFiled: December 3, 1998Date of Patent: February 8, 2000Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yuh-Da Fan