Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.

Abstract: A method of forming a conductive metal silicide by reaction of metal with silicon is described. A method includes providing a semiconductor substrate with an exposed elemental silicon-containing surface. At least one of a nitride, boride, carbide, or oxide-comprising layer is atomic layer deposited onto the exposed elemental silicon-containing surface to a thickness no greater than 15 Angstroms. This ALD-deposited layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal-rich silicide is deposited onto the plasma-exposed layer. Metal of the conductive reaction layer is reacted with elemental silicon of the substrate effective to form a conductive metal silicide-comprising contact region electrically connecting the conductive reaction layer with the substrate. Other aspects and implementations are contemplated.

Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a cap

Abstract: Described is a method for fabricating a capacitor of a semiconductor device. The method includes the steps of forming an insulating interlayer including a storage node contact hole on a semiconductor substrate, forming a polysilicon layer on the insulating interlayer including the storage node contact hole, and forming a sacrificial resist layer on the polysilicon layer, thereby filling the storage node contact hole with the sacrificial resist layer.

Abstract: According to one embodiment of the invention, a method for planarizing bumped die includes providing a die having a plurality of stud bumps, encapsulating the stud bumps with an epoxy-based material, and disposing a release layer outwardly from the epoxy-based material. A surface of the release layer that engages the epoxy-based material is substantially planar. The method further includes curing the epoxy-based material and removing the release layer after the curing step, thereby creating a substantially planar surface of the epoxy-based material.

Abstract: After a plurality of grooves are formed in an insulating film and in an antireflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the grooves is filled. Subsequently, the portions of the conductive film outside the grooves are removed by a first polishing step and then the portions of the barrier metal film outside the grooves are removed by polishing. Thereafter, foreign matter adhered to the surface of the anti-reflection film is removed and a third polishing step is conducted on the surface of the anti-reflection film using an abrasive agent of the same type as used in the first polishing step of the conductive film.

Abstract: A method for forming a bit line of a semiconductor device wherein a first opening in an interlayer insulation film is formed in a P+ S/D (source/drain) region, a post etch treatment (PET) for stabilizing the resistance in the P+ S/D opening is performed, followed by the subsequent formation of a second opening in the N+ S/D region, such that any increase of the resistance of the N+ S/D opening by the PET is thereby prevented.

Abstract: A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by the multilayered doped conductor is less suspectible to depletion from trapped charges in the oxide. This improves device reliability at burn-in and lowers junction leakage, thereby providing a longer period between refresh cycle.

Abstract: A method for monitoring a dose of a silicon bearing implant is described. The method includes introducing a first implant species through a surface of a semiconductor substrate at a first does of energy level and introducing a silicon bearing species through the surface of the semiconductor substrate at a second dose and a second energy level. The method anneals the semiconductor substrate and measures a sheet resistance value of the surface of the semiconductor substrate. The method also determines the second dose value based upon the surface resistance value.

Abstract: A method for manufacturing microelectronic device packages. In one embodiment, the device package can include a support member having a first surface, a second surface facing opposite the first surface and a cavity extending through the support member from the first surface to the second surface. A microelectronic device is disposed in the cavity and is supported in the cavity with a removable retention member. The microelectronic device is electrically coupled to the support member and is partially surrounded with an encapsulating material. The removable retention member is then removed to expose a surface of the microelectronic device. Accordingly, the package can have a low profile because the encapsulating material does not surround one of the microelectronic device surfaces. In one embodiment, a heat conductive material can be engaged with the exposed surface of the microelectronic device to increase the rate at which heat is transferred away from the microelectronic device.

Abstract: A method for fabricating thin films of an icosahedral boride on a silicon carbide (SiC) substrate is provided. Preferably the icosahedral boride layer is comprised of either boron phosphide (B12P2) or boron arsenide (B12As2). The provided method achieves improved film crystallinity and lowered impurity concentrations. In one aspect, an epitaxially grown layer of B12P2 with a base layer or substrate of SiC is provided. In another aspect, an epitaxially grown layer of B12As2 with a base layer or substrate of SiC is provided. In yet another aspect, thin films of B12P2 or B12As2 are formed on SiC using CVD or other vapor deposition means. If CVD techniques are employed, preferably the deposition temperature is above 1050° C., more preferably in the range of 1100° C. to 1400° C., and still more preferably approximately 1150° C.

Abstract: A method of manufacturing a semiconductor device is provided. A nickel silicide layer (e.g., NiSi) is formed on a substrate. Next, a hydrogen plasma treatment may be performed on the silicide layer, which may induce the formation of metal/silicon hydride bonds in the silicide layer. An etch stop layer is formed over the silicide layer. A dielectric layer is formed over the etch stop layer. An opening is formed in the dielectric layer. A portion of the etch stop layer is etched away at the opening to expose at least a portion of the silicide layer therebeneath. The etch chemistry mixture used during the etching step preferably includes hydrogen gas. The change in sheet resistance for the exposed silicide layer portion at the opening after the etching step, as compared to before the etching step, is preferably not greater than about 0.10 ohms/square.

Abstract: A fabrication method for a silicon nitride read only memory includes sequentially forming a tunneling oxide layer and a charge capture layer on a substrate. An isolation region is formed in the charge capture layer to partition the charge capture layer into a plurality of charge capture blocks. A stacked dielectric layer is then formed on the charge capture layer and the isolation region. Thereafter, the stacked dielectric layer and the charge capture layer are patterned to expose regions of the substrate for forming bit lines, followed by forming a field oxide layer and a control gate.

Abstract: A method for the production of semiconductor components which includes applying masking layers and components on epitaxial semiconductor substrates within the epitaxy reactor without removal of the substrate from the reactor. At least one of the masking layers is HF soluble such that a gas etchant may be introduced within the reactor so as to etch a select number and portion of masking layers. This method may be used for production of lateral integrated components on a substrate wherein the components may be of the same or different type. Such types include electronic and optoelectronic components. Numerous masking layers may be applied, each defining particular windows intended to receive each of the various components. In the reactor, the masks may be selectively removed, then the components grown in the newly exposed windows.

Abstract: A method for characterizing a dose or dosage of implanted atomic species in a substrate by annealing the substrate after implantation of the atomic species, with the anneal conducted at a temperature and for a time sufficient to cause the implanted atomic species to from blisters in a surface region of the substrate but below that which would cause a majority or significant amount of the blisters to burst; imaging the surface region of the substrate to obtain a surface image; and processing the surface image to characterize the implant dose of the atomic species. This characterization can be performed on a qualitative or quantitative basis, as desired.

Abstract: After a silicidation blocking pattern is formed on a substrate including silicon, the silicidation blocking pattern is hardened by a thermal annealing process. The substrate is rinsed to remove a native oxide film formed on the substrate, and then a silicide film is formed on a portion of the substrate exposed by the silicidation blocking pattern. The silicide film can thus be formed in an exact portion of the substrate, and the substrate is not damaged during rinsing.

Abstract: Various embodiments are methods and apparatuses for different steps in separating wafers into multiple wafer die. Some embodiments are adapted for dicing wafers having a front side and a back side, where the front side has processed devices, such as MEMS devices.

Abstract: A preferred condition for forming a Group III nitride compound semiconductor layer on a substrate by a sputtering method is proposed. When a first Group III nitride compound semiconductor layer is formed on a substrate by a sputtering method, an initial voltage of a sputtering apparatus is selected to be not higher than 110% of a sputtering voltage.

Abstract: A method of forming a charge balanced, silicon dioxide layer gate insulator layer on a semiconductor substrate, with reduced leakage obtained via nitrogen treatments, has been developed. Prior to thermal growth of a silicon dioxide gate insulator layer, negatively charged fluorine ions are implanted into a top portion of a semiconductor substrate. The thermal oxidation procedure results in the growth of a silicon dioxide layer with incorporated, negatively charged fluorine ions. Subsequent nitrogen treatments, used to reduce gate insulator leakage, result in generation of positive charge in the exposed silicon dioxide layer, compensating the negatively charged fluorine ions and resulting in the desired charge balanced, silicon dioxide gate insulator layer.

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.