Abstract: Methods of forming vertical MOSFETs include forming a base region of second conductivity type in a semiconductor substrate having a drift region of first conductivity type therein that forms a P-N junction with the base region. A source region of first conductivity type is formed in the base region and a deep trench, having a first sidewall that extends adjacent the base region, is formed in the substrate. The deep trench is lined with a first electrically insulating layer. The deep trench is then refilled with a trench-based source electrode. The trench-based source electrode is selectively etched to define a shallow trench therein and expose a first portion of the first electrically insulating layer that extends on the first sidewall of the deep trench. The first portion of the first electrically insulating layer is selectively etched to expose an upper portion of the first sidewall of the deep trench and reveal the base region.

Abstract: An aluminium film is formed by sputtering on a ferromagnetic layer made of, e.g., Ni—Fe alloy. The aluminum film is oxidized while an alumina film is deposited on the aluminum film by reactive sputtering, to form a tunneling barrier film. Assuming that the aluminum film has a thickness of 1 nm and the alumina film deposited has a thickness of 0.2 nm, an alumina film having a thickness of about 1.5 nm is formed on the ferromagnetic layer, this alumina film being a lamination of an alumina film which is the oxidized aluminum film and the deposited alumina film. The surface of the ferromagnetic layer is prevented from being oxidized because of the presence of the aluminum film. A thin oxide film such as alumina can be formed in a short time without oxidizing an underlying layer.

Abstract: A method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process including providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process. The capping layer of the present invention has improved adhesion and a reduced dielectric constant with comparable current leakage compared to capping layers of the prior art.

Abstract: In a method for making transistors with ultrashort channel length, the deposition of respectively source, drain and gate electrodes initially can be performed with prior art technology limiting the electrode dimensions according to applicable design rules, while the dimensions of every second of these electrodes in subsequent process steps can be adjusted as desired. A channel area is formed between a source and a drain electrode without being constrained by any design rule and this allows the formation of transistor channels with extremely short channel lengths L, e.g. well below 10 nm. Correspondingly the width of the gate electrodes can be adjusted to also obtain a large channel width W and hence provide transistors with almost arbitrarily large aspect ratios W/L and thus desirable switching and current characteristics. The method can be applied to make any kind of field-effect transistor, even on the same substrate and may be adjusted for the fabrication of other kinds of transistor structures as well.

Abstract: An improved and novel magnetic element and fabrication method. The magnetic element (10;30) including a bottom pinned ferromagnetic layer (12;32) and a top pinned ferromagnetic layer (20;40) fabricated antiparallel to one another. The magnetic element (10;30) further including a bottom tunnel barrier layer (14;34), a free ferromagnetic layer (16;46 and 48) and a top tunnel barrier layer (18;38) formed between the bottom pinned ferromagnetic layer (12;32) and the top pinned ferromagnetic layer (20;40). The structure is defined as including two (2) tunnel barrier layers in which one tunnel barrier layer is normal (18) and one is reversed (14), or a structure in which the two tunnel barrier layers are of the same type (34; 38) with the structure further includes a SAF structure (36) to allow for consistently changing magnetoresistance ratios across both tunnel barriers. The magnetic element (10;30) having an improved magnetoresistance ratio and a decrease in voltage dependence.

Abstract: A method for forming an active area in a substrate includes the steps of growing an isolation oxide on a silicon substrate, providing a photresist mask to define the active areas on the substrate, performing etching and stripping processes, removing the residual oxide from the active areas and selectively growing an epitaxial silicon layer.

Abstract: A method for removing a carbon-containing polysilane from a semiconductor substrate without stripping the polysilane during manufacture of a semiconductor device, the method entailing the steps in the following order of coating a carbon-containing polysilane on a semiconductor substrate and coating a resist on the polysilane; patterning the resist with exposure and development; transferring the pattern from the resist to the polysilane using an etch process selective to the resist; stripping the resist; transferring the pattern from the polysilane to a hardmask using an etch selective to the hardmask; subjecting the polysilane to thermal or plasma/thermal oxidation to convert the polysilane to silicon oxide; and etching the substrate and stripping off the hardmask.

Abstract: The invention provides a method for forming a ferroelectric thin film that is uniform and good in crystallinity. The method includes applying a liquid to a surface of a substrate. The liquid includes ultra-fine particle powder comprising at least one element constituting the ferroelectric thin film to a surface of a substrate. The liquid applied to the surface of substrate is then baked.

Abstract: A method and apparatus for connecting a die having active circuitry to a substrate in semiconductor applications and in thermal inkjet printer applications where the die is directly bonded and sealed to the substrate without the need for conventional TAB circuit. Each die includes a back-side and a front-side, where the active circuitry is positioned, with at least one through-hole formed between the front-side and the back-side of the die. Each through-hole on the die is aligned with a corresponding conductive trace on the substrate. A conductive member is inserted within each through-hole. One end of the conductive member is electrically connected to a trace on the substrate. The other end of the conductive member is inserted into the through-hole such that the conductive member is positioned through the die and is exposed at the front-side of the die to contact an interconnect pad, which is electrically connected to the active circuitry on the die.

Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

Abstract: A method for forming an opening through an interlayer to expose an underlying surface that retains high etch selectivity while having a relatively large process window to accommodate process variations. The method etches an interlayer under a first etching condition that forms a protective layer over portions of exposed surfaces of the opening during the etch process. The formation of the protective layer continues until an etch stop condition is produced, stopping further etching of the interlayer under the first condition prior to exposing the underlying surface. The method continues with etching through the protective layer under a second etching condition to expose a residual interlayer, and etching the exposed residual interlayer under the second etching condition to expose the underlying surface.

Abstract: The present invention relates to a method for depositing metal layers on substrates with improved surface morphology. According to one aspect of the invention, a metal is deposited by chemical vapor deposition on a substrate having an aperture formed therein. A metal is then deposited on the substrate by physical vapor deposition performed with a low substrate temperature. The substrate is then heated. The substrate may then receive a metal deposited by physical vapor deposition performed at a high temperature and an additional heating step. The aperture of the resulting substrate is filled with metal and is substantially void-free and has a smooth surface morphology.

Abstract: After first metal lines and a first inter-metal dielectric are formed on a semiconductor substrate, top surfaces thereof are planarized to construct a flat plane. Then, second metal lines each being vertically aligned with a corresponding first metal line are formed on the flat plane, so that integral metal lines of a high aspect ratio are constructed. Gaps formed by the second metal lines are filled with a second inter-metal dielectric, which is joined with the first inter-metal dielectric to construct an integral inter-metal dielectric.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen oxide plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Abstract: A method and structure for increasing the area and capacitance of both trench and planar integrated circuit capacitors uses Si nodules deposited on a thin dielectric seeding layer that is absorbed during subsequent thermal processing, thereby avoiding a high resistance layer in the capacitor.

Abstract: An improved source/drain extension process is provided by the following processing steps of implanting NMOS devices directly on either side of the gates without an oxide layer (step D2), covering the gates with a cap oxide layer(step E2), covering NMOS devices with photoresist(step F2), dry etching all PMOS devices (Step G2), and implanting PMOS devices (step I2).

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: In a flip-chip type semiconductor device, a plurality of pad electrodes are formed on a semiconductor substrate. An insulating stress-absorbing resin layer made of thermosetting resin is adhered to the substrate as a composite layer in conjunction with a first conductive layer and has openings corresponding to the pad electrodes. A plurality of metal bumps are formed on the conductive layer.

Abstract: A unique photoresist strip sequence using a downstream plasma system is described. The sequence can include a RF directional plasma alone, downstream plasma alone or combine both RF plasma and downstream plasma together. The process sequence can be a single step or multiple steps, which produce high strip rates while maintaining the dielectric properties of the film. The process can be an oxidizing process carried out at low temperature and low pressure, which reduces the reactivity of the oxygen with the low-k film. Furthermore, by adding a small percentage of an additive gas, such as a fluorine-containing gas, to the plasma, the inorganic residues from the strip process are removed, leaving a clean film cleared of photoresist and residue.

Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region including P/N junction formed of a first semiconductor region with a first type of conductivity, which first semiconductor region extends through the substrate from the top surface of the device and is diffused into a second semiconductor region with the opposite conductivity from the first. The device also includes an interface structure between the two regions, of substantial thickness and limited planar size, that includes a trench filled with dielectric material. A method of manufacturing the electronic power device includes forming a silicon oxide-filled trench. The method includes forming, in the substrate, a plurality of small trenches having predetermined widths and -being delimited by a corresponding plurality of semiconductor material walls having second predetermined widths.