Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A process of dual damascene or damascene. The dual damascene process entails providing an etching apparatus, a DCM machine and a wafer, the wafer having a metal line, a stop layer, a dielectric layer, a contact, and a photoresist layer. The dielectric layer and the contact are etched in the etching apparatus to form a trench. The photoresist and the contact are ashed in the DCM machine. Finally the wafer is wet cleaned.

Abstract: The invention is directed to a fabrication method of copper interconnects using dual damascene processing. Using silicon to provide an active surface, palladium can be selectively deposited on silicon by an immersion plating technique. After palladium deposition (about 1000 Å thick), either a layer of cobalt phosphorus or alloy cobalt/nickel phosphorus or nickel phosphorus is deposited on the palladium layer using an electroless plating technique. This cobalt phosphorus, cobalt/nickel phosphorus alloy, or nickel phosphorus layer serves as a copper diffusion barrier. The via and trenches are filled with copper by an electroless copper plating method and CMP is used to remove the excess copper and planarize-/-polish the copper/dielectric surface.

Abstract: Described is a method for fabricating ceramic chip packages in which an epoxy resin containing fine ceramic particles is applied on a ceramic substrate provided with chip packages respectively having a plurality of chips mounted thereon, thereby improving reliability and endurance of the package and miniaturizing the size of the package. The epoxy resin is applied on the ceramic substrate provided with a plurality of the chips mounted thereon except a designated region, thereby minimizing the deformation of the substrate. The epoxy resin layer is formed on the substrate by two steps including a first step for forming a first epoxy resin layer serving as a dam and a second step for forming a second epoxy resin layer, thereby reducing the amount of the used epoxy resin and improving reliability and endurance of the package against temperature and humidity.

Abstract: A method of manufacturing a non-volatile semiconductor memory device, including forming a first gate insulating film, on a semiconductor substrate; forming a first conductive layer as the lowest layer of a charge-storage layer on the first gate insulating film; forming a masking material on the first conductive layer; etching the masking material, the first conductive layer, the first gate insulating film and the substrate so that side end portions thereof meet each other to form a trench; oxidizing a side wall of the trench and a side-wall surface of the first conductive layer; filling the trench with an isolation insulating film; exposing and peeling off the masking material to expose the upper surface of the first conductive layer; depositing a second conductive layer, which is the highest layer of the charge-storage layer, on the substrate; flattening the second conductive layer to be flush with the upper surface of the isolation insulating film; forming a second gate insulating film on the second conduct

Abstract: A method for fabricating a semiconductor device is described in which isolation layers and a collector of a BJT are simultaneously formed by an epitaxtial growth process during a process of fabricating a BiCMOS. The method for fabricating a semiconductor device of the present invention includes processes of forming a first mask layer on a semiconductor substrate, etching a predetermined portion of the semiconductor substrate with predetermined depth using the first mask layer, forming a first isolation layer on a side face of the etched semiconductor substrate, forming a first epitaxial layer doped with a plurality of layers by epitaxial growth of the exposed portion of the semiconductor substrate, forming a second mask layer on the first epitaxial layer, and forming a second epitaxial layer by epitaxial growth of a portion of the first epitaxial layer.

Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.

Abstract: The invention provides a method for readily forming a bump with a desired width, a semiconductor device and a method for making the same, a circuit board, and an electronic device. A method for forming a bump includes forming an opening in an insulating film which exposes at least a part of a pad, and forming the bump so as to be connected to the pad. A resist layer 20 defines a through hole which extends over at least a part of the pad in plan view. A metal layer is formed in the opening so as to connect to the exposed portion of the pad.

Abstract: A method of manufacturing a semiconductor device includes forming a bump projecting from a first surface of a semiconductor chip, and forming a conductive layer so that part of the conductive layer is exposed at a position depressed from a second surface of the semiconductor chip opposite to the first surface, wherein the exposed part of the conductive layer and the bump become electrical connecting sections.

Abstract: A method for forming a polyatomic layer with a mixed deposition method consisting of an atomic layer deposition method (ALD) and a chemical vapor deposition method. The mixed deposition method can be adopted to form a polyatomic high dielectric layer, such as BST or STO. Accordingly, it is possible to form a polyatomic high dielectric layer having a uniform composition distribution, and thereby also having a high dielectric characteristic and a low leakage current characteristic.

Abstract: A dielectric film containing lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric film is formed by ion assisted electron beam evaporation of TiO2 and electron beam evaporation of a lanthanide selected from a group consisting of Nd, Tb, and Dy. The growth rate is controlled to provide a dielectric film having a lanthanide content ranging from about ten to about thirty percent of the dielectric film. These dielectric films containing lanthanide doped TiOx are amorphous and thermodynamically stable such that the lanthanide doped TiOx will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.

Abstract: A method of forming shallow trench isolation in a semiconductor substrate. A hard mask having an opening is formed on the semiconductor substrate. The semiconductor substrate is etched through the opening to form a shallow trench. The semiconductor substrate such as silicon substrate is annealed in an ambient containing nitric oxide or nitrogen and oxygen to form a silicon oxynitride film on the shallow trench to serve as a barrier to prevent dopant source/drain outdiffusion. An insulator is then formed on the hard mask to fill the shallow trench. The insulator is planarized while the hard mask is used as the polishing stop layer. Thereafter, the hard mask is removed to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation.

Abstract: Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.

Abstract: Process for stripping photoresist from a semiconductor wafer formed with at least one layer of OSG dielectric. The stripping process may be formed in situ or ex situ with respect to other integrated circuit fabrication processes. The process includes a reaction may be oxidative or reductive in nature. The oxidative reaction utilizes an oxygen plasma. The reductive reaction utilizes an ammonia plasma. The process of the present invention results in faster ash rates with less damage to the OSG dielectric than previously known stripping methods.

Abstract: Provided are flip chip device assembly methods that integrate the solder joining and underfill operations of the assembly process. Solder joining of the die and substrate and curing of the underfill material between the die and substrate is accomplished in the same heating and cooling operation. As a result, the coefficient of thermal expansion (CTE) mismatch stresses incurred prior to application and curing of underfill by a device packaged according to the conventional technique having a separate heating and cooling operation following solder joining, are avoided. These stresses are of particular concern in smaller device size technologies (e.g., 0.13 microns and smaller) using low k dielectrics and large die sizes due the difference in CTP between the die and substrate.

Abstract: A conductive element of an integrated circuit wiring network is formed by a plating process. A seed layer for the conductive material is grown on the sidewalls and bottom surface of a trench using a low energy ion implantation process. The implantation is performed at an angle to the substrate to achieve coverage of the trench sidewalls. The resulting seed layer avoids constricting or closing the opening of the trench and has an approximately uniform thickness.

Abstract: Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.

Abstract: In a flip-chip type semiconductor device, a plurality of pad electrodes are formed on a semiconductor substrate. An insulating stress-absorbing resin layer made of thermosetting resin is formed on the semiconductor substrate and has openings corresponding to the pad electrodes. A plurality of flexible conductive members are filled in the openings. A plurality of metal bumps are formed on the flexible conductive layers.

Abstract: A semiconductor device is manufactured using a SiC substrate. On a semiconductor region a region formed of SiC having an (11-20) face orientation is formed. A gate insulation layer is a gate oxidation layer. The surface of the semiconductor region is cleaned, and the gate insulation layer is formed in an atmosphere containing hydrogen or water vapor. After the gate insulation layer has been formed, the substrate is heat-treated in an atmosphere containing hydrogen or water vapor. This reduces the interface-trap density at the interface between the gate oxidation layer and the semiconductor region.