Abstract: A method for improving the corrosion resistance of aluminum in a semiconductor device. The step includes providing a semiconductor device having aluminum containing contact pads; attaching a leadframe to the contact pads; and applying sufficient zinc chromate in solution to the contact pads for a sufficient time and at a sufficient temperature to render said aluminum substantially resistant to corrosion.

Abstract: The present invention provides a method for protecting integrated circuit packages mounted on carrier tapes during manufacturing steps commonly employed in tape automated bonding processes. A reel is provided for winding the carrier tape into a compact package. A steel tape with corrugated longitudinal edges is also provided for winding on the reel in alternating layers with the carrier tape. The carrier tape thus is framed, layer by layer, with the steel tape, thus protecting each integrated circuit package from coming into contact with another object during manufacturing steps, e.g. heat curing.

Abstract: A process for forming an integral circuit pin grid array package comprising a flexible metal tape adapted for use in tape automated bonding with a plurality of holes. Terminal pins are inserted in the holes and the tape and pins are disposed within a mold so that a cavity is formed about the pins and tape. The cavity is filled with a polymer resin so as to at least partially surround and support the pins and tape and thereby form the plastic encapsulated pin grid array.

Abstract: A semiconductor chip mounting is provided by molding a substrate of heat resistant synthetic resin, forming contact pads, which may be protrusions or recesses, on a surface of the substrate as it is molded. A circuit pattern extends to the contact pads which have a conductive surface. The chip is directly mounted on the substrate by soldering contact areas on the chip to the contact pads on the substrate, thus avoiding wire bonding.

Abstract: A method for providing increased dopant concentration in selected regions of semiconductors by providing field implant dopant in the transition region located below the "bird's beak" region and between the field and active regions of a semiconductor. The method comprises the steps of: forming a thin insulating layer on the surface of a semiconductor substrate; depositing a thin anti-oxidant layer on the insulating layer; depositing a layer of photoresist on the anti-oxidant layer; selectively etching the anti-oxidant layer; ion-implanting the field region of the semiconductor substrate; providing spacers on the sides of the anti-oxidant layer; and oxidizing the semiconductor substrate.

Abstract: A method for the discretionary interconnection of plural devices into an array includes the steps of designing bridge sites between the devices, individually testing the devices, inking over the bridge sites to devices which do not meet predetermined parameters, and soldering in a manner to cause the solder to bridge the gap between the acceptable devices and the rest of the array but not to bridge the gap to unacceptable devices. In devices comprised of multiple parallel elements, only sub-elements which fall within predetermined functional requirement ranges are incorporated into the parallel array produced. This method of discretionary interconnection is readily adapted to automated techniques for fabricating semiconductor MOS devices such as MCTs, IGBTs and parallel MOSFET arrays.

Abstract: A TAB (Tape Automated Bonding) process uses single-layer tapes to form a semiconductor structure. Beam leads on a metal tape are "inner-lead bonded" to a chip. Each chip site on a specially-formed plastic tape has a central portion and a peripheral portion which are bonded to the chip so that the central portion forms a protective cover over the chip and the peripheral portion acts as a support for the beam leads during probe testing, excising and forming operations, etc. The bottom surface of the chip preferably remains uncovered so that it can, if appropriate, be electrically connected to ground or another potential.

Abstract: A via connection and method for making the same for integrated circuits having multiple layers of electrically conductive interconnect lines separated by an insulative layer. The via connection is characterized by a very thin layer of high resistivity material lining the via hole in conductive contact with interconnect lines in two layers. The resistivity of the thin layer material is in a range from about 10 to about 50 times the interconnect line resistivities and generally has a thickness of less than 100 nanometers. The thin layer assures more uniform current flow in the via connection thereby preventing electromigration, with reduced peak local current density by causing current to swing more widely around the corner at the interface between the interconnect lines at the via.

Abstract: A method of producing a semiconductor device having a light transparent window, includes: a process of die bonding a chip onto a lead frame; a process of attaching a wall surrounding a picture element to either of the external contour surface of the surface of the chip or the light transparent window surrounding the picture element; a process of inserting the chip and the light transparent window into a metal mold in such a manner that an empty closed space is produced between the chip and the light transparent window via the wall; and a process of plastic molding the device except for the light transparent window by filling resin into the metal mold and making the resin hardened.

Abstract: In order to secure electronic components, and particularly large-area power semiconductors, to a substrate, first a paste formed of metal powder and a solvent is applied in the form of a layer to a contacting layer of the component and/or a contact surface of the substrate. The layer of paste is then dried. When the paste has dried, the component is placed onto the substrate, whereupon the entire arrangement is heated to a relatively low sintering temperature preferably between 180.degree. C. and 250.degree. C., and with simultaneous application of a mechanical pressure of at least 900 N/cm.sup.2. A connection which is thus achieved by such a pressure sintering at relatively low sintering temperatures is particularly suitable for securing power semiconductors produced in MOS-technology to a substrate.

Abstract: A process of forming a conductive material layer in at least two steps by forming a conductive material layer from a plurality of thin layers of conductive material. The use of a two-step formation process for the conductive material layer permits process versatility in incorporating implantation steps and patterning steps between formation of the thin layers of conductive material. Direct transfer from dielectric layer formation to conductive material layer formation steps, and performing the intermediate process steps in the same piece of equipment as the thin conductive layer formation assists in adhesion of the thin layers to each other to form the total conductive material layer. The use of in situ doped semiconductor material, such as in situ doped polycrystalline silicon and in situ doped amorphous silicon reduces the exposure of other dopants that may be present to thermal cycles of high temperature, greater than 900.degree. C., that causes these dopants to migrate undesirably.

Abstract: A method for the replacement of semiconductor devices in a multi-chip module that is constructed by mounting semiconductor devices on a tape carrier used as an electrical wiring substrate, wherein when at least one of said semiconductor devices develops a flaw, it is cut away at the finger sections that connect said defective semiconductor device to the tape, and then a different and non-defective semiconductor device having finger sections longer than those of said defective semiconductor device that has been removed is connected to said tape in such a manner that the finger sections of said different and non-defective semiconductor device are joined and connected to the corresponding finger sections retained on said tape.

Abstract: The copper tape that is used in the tape assembly of semiconductor devices is provided with a bondable surface by an electroplated layer of copper. The copper tape is passivated in a weak organic acid solution immediately after plating. In the preferred embodiment the copper tape is also cleaned and passivated prior to electroplating. The passivated copper can be thermosonically bonded using gold wires for up to 144 hours after preparation. The elimination of noble metal plating reduces assembly cost and the passivated copper bonds well to the subsequently applied plastic encapsulant.

Abstract: A method for fabricating a semiconductor device comprises forming a contact hole in an insulating film formed on a first wiring composed of an Al film, covering the insulating film with an Al film for a second wiring, applying laser beam pulses to the Al film for a second wiring from above, and patterning the Al film to form a second wiring.

Abstract: A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist over the backside of the gallium arsenide substrate, and this layer is patterned to provide selected areas covering regions where tub structures and vias will be provided. In the selectively exposed regions, palladium and gold are sequentially deposited. The resist pattern is then stripped, and a second resist layer pattern is deposited masking portions of the continuous conductive layer and areas where vias are to be provided. The tub structures are then provided by suitably etching the tub to undercut portions of the resist and the palladium layer. A second continuous conductive coating is then provided in the tub structure to provide a plating layer for subsequent plating of a gold film over the palladium.

Abstract: According to the present invention, a tape carrier is prepared which comprises a power trunk line including an electric connection as a branch of a power lead for each tape carrier unit and a ground trunk line having an electric connection as a branch of a ground lead for each tape carrier unit, the power and trunk lines being continuously formed along the longitudinal direction of the tape carrier, and a lead for a control signal for establishing an electric conduction along the longitudinal direction of the tape carrier via an aging wiring for semiconductor pellets to conduct a simultaneous multipoint (gang) bonding on the tape carrier. By mounting the semiconductor pellets having the aging wiring on the tape carrier, it is enabled to apply the power voltage and to supply the control signal to each of the plurality of the semiconductor pellets, and hence the operation test can be simultaneously conducted for the semiconductor pellets mounted on the tape carrier having an arbitrary length.

Abstract: A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.

Abstract: A method for fabricating a thin-film transistor having a stagger structure, in which the inner portion of the amorphous silicon layer doped as an ohmic contact layer to source and drain areas is defined by an insulating layer interposed therebetween, a step for forming source and drain electrodes on said amorphous silicon layer, which comprises a film forming process for forming a metal layer; a thermal treatment process for heating so as to generate a surface reaction between said metal layer and said amorphous silicon layer in order to selectively form a reaction layer only on said amorphous silicon layer; and a patterning process for selectively removing said metal layer so as to form source and drain electrodes.

Abstract: An improved hermetically sealed semiconductor casing and a process for producing the casing are disclosed. This casing includes a lead frame having an electrical device affixed thereto. A base member is glass bonded to a matching surface of the lead frame. A metal window frame shaped device is provided having one surface with a refractory oxide coating and a second opposite readily solderable surface. The refractory oxide layer of the window frame device is glass bonded to the lead frame and the base member. The semiconductor or electrical device is connected to the lead frame after the window frame has been glass bonded into place. A metal lid having a solderable surface is solder bonded to the solderable surface of the window frame to hermetically seal the electrical device within the casing.

Abstract: A method is disclosed for forming a detector device, such as a thinned bulk silicon blocked impurity transducer infrared detector, by thinning a semiconductor substrate (10) and processing the thinned region (30) on two sides to form the detector device. The semiconductor substrate (10) is thinned to form a cavity (26) in the substrate (10). Further processing on both sides of the thinned region (30) is performed while the thinned region is still connected to the thicker substrate. The thinned region (30) is then separated from the substrate (10) upon completion of the given processing steps. The device is then mounted to a readout device (58).