Abstract: The present invention is a method for packaging and protecting an integrated circuit chip on a carrier tape. A carrier tape comprising at least two bonded layers (one layer being made of an electrically conductive material) includes small flat leads in the conductive layer. A carrier bridge or frame of nonconductive material is bonded to one surface of the leads and is connected to a nonconductive layer (or a part of) the tape. The electrical pads of an integrated circuit are bonded to the respective leads of the tape simultaneously. The leads are cut at a predetermined length from the chip and outside of the frame. The lead ends are bent to form a nest. A planar base is adehered to the surface of the chip having the electrical pads. The leads are then bent over the base to secure the base on the tape and provide electrical contact points to the chip. The chip is coated with a suitable material and to provide insulation and encapsulation of the entire packaging structure.

Abstract: A technique for enclosing microelectronic circuit elements in hermetically sealed packages comprising a planar ceramic substrate with a box-like ceramic cover sealed thereto by a fused glass coating. The glass sealant is applied to the substrate in the form of a paste which thereafter is fired at high temperature and cooled to produce a smooth glass coating. With the cover in place on the substrate, the glass coating is remelted by heat developed by infra-red radiation developed by four line-focussed radiant heaters at the four sides of the package. The radiation of each heater is focussed at the interface line between the cover and the substrate. Because the radiant heat is concentrated along the interface line, unwanted heat transfer into the package is minimized, and the temperature is prevented from rising sufficiently to damage heat-sensitive elements.

Abstract: A semiconductor device is provided within an outer container (21) made of a ceramic which is of a box shape having an opening in an upper portion thereof and a bottom plate and also having a stepped portion (21a) at the position in an intermediate height of an inner wall of side plates. A metalized layer (22) is deposited in inner and outer surfaces of the bottom plate and a surface of the stepped portion. A metal plate (30) is brazed by a silver solder (26) on the metalized layer of the outer surface of the bottom plate and at the same time, a common metal substrate (27) is also brazed by a silver solder (26) on the metalized layer (22) on the inner surface of the bottom plate. A plurality of external electrodes (23, 23', 24, 25) in a frame shape of a conductor plate are connected to the metalized layer (22) of the surface of the stepped portion (21a) by a silver solder (26).

Abstract: The invention relates to microcircuit cards, used for electronic transactions or other purposes, and concerns a process for mass producing electronic modules to be used in these cards and the modules obtained according to this process. According to the invention, there are fabricated, on the one hand, a metal grid with a plurality of openings into which there penetrate tongues attached to the frame of this grid and intended to form the modules' contact areas, and, on the other hand, pellets of plastics material which have a generally flat front face, a rear face in which there is a hollow and, between this hollow and the front face, windows so arranged that they can be positioned opposite the grid tongues.

Abstract: A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. A layer of planarizing material is deposited over the silicon layer. The planarizing layer is anisotropically etched until the surface of the silicon layer overlying the island is exposed. The silicon layer is in turn etched until the surface of the oxide layer overlying the island is exposed. The remaining planarizing material is removed and the remaining silicon layer is oxidized. The thickness of the gate oxide layer on top of the island may be controlled by again exposing the island surface and reoxidizing to a predetermined thickness. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

Abstract: In the manufacture of a packaged IC chip, a lead frame segment has a plurality of leads, the ends of which are connected to opposing rails. After the leads are secured to a lead frame support, the rails are removed and an IC chip is then connected. The chip and lead frame are then encapsulated between the support and a cover.

Abstract: A layer of HgCdTe (15) is epitaxially grown onto a CdTe substrate (5). A HgTe source (3) is spaced from the CdTe substrate (5) a distance of between 0.1 mm and 10 mm. The substrate (5) and source (3) are heated within a temperature range of between 500.degree. C. and 625.degree. C. for a processing step having a duration of between 5 minutes and 4 hours. During at least 5 minutes of this processing step, the substrate (5) is made to have a greater temperature than the source (3). Preferably the substrate (5) is never at a lower temperature than the source (3). The source (3) and substrate (5) are heated together in a thermally insulating, reusable ampoule (17). The CdTe substrate (5) is preferably a thin film epitaxially grown on a support (10) e.g., of sapphire or GaAs. When support (10) is not used, the CdTe substrate (5) is polished; and sublimation and solid state diffusion growth mechanisms are present in the growth of the HgCdTe (15).