Abstract: A flat LED panel display with LED elements arranged in a high density and a method of producing such a display are disclosed. A conductive layer is deposited on a ceramic substrate and bonded to one surface of an LED wafer by a conductive paste. A plurality of electrodes are arranged on the other surface of the LED wafer in rows and columns to define a two-dimensional pattern. Slits are formed along the rows or the columns each to a depth which extends from the other surface of the LED wafer to the ceramic substrate. Other slits are formed perpendicular to the first-mentioned slits each with a depth which extends from the other surface of the LED wafer to a position deeper than it but short of the ceramic substrate.

Abstract: A monolithic silicon integrated circuit chip is provided with a conductive passivating coating over the metal bonding pads. The coating is composed of doped polysilicon or metal silicide. Such materials provide a self-passivating, non-corrodable surface capable of forming a conventional eutectic bond to a connecting wire. A moat is etched through this layer outside the confines of the bonding pad so that they can be electrically isolated. Eutectic wire bonds are then made to the coating where they would ordinarily be made to the pad metal. Since the passivating coating fully covers the bonding pad a substantial increase in passivation occurs. If desired the passivating coating can be overcoated with a thin metal layer to facilitate probing of the circuits in wafer form.

Abstract: A method for forming a silicon dioxide layer on a silicon island on an insulating substrate includes the steps of initially providing an insulating substrate having a major surface on which a silicon island is disposed. The surface of the silicon island is then thermally oxidized and a silicon layer is deposited on the oxidized island and the portion of the substrate surface adjacent to the island. This entire silicon layer is then oxidized and a conductive polycrystalline silicon electrode is deposited thereon.

Abstract: A semiconductor contact system controls the boundary recombination velocity and optimizes the semiconductor transport phenomena and includes a microcrystalline layer of doped semiconductor microcrystals surrounded by a semiconductor oxide. The microcrystalline layer is acceptor and oxygen doped to provide unipolar hole transport and donor and oxygen doped to provided unipolar electron transport. The oxygen doping is implanted several atomic layers into the semiconductor to form a gradient between the semiconductor and microcrystalline layer to preserve the semiconductor monocrystalline lattice. The thickness of the microcrystalline film is adjusted to be thick enough to control the effective chemostatic potential terminating the semiconductor and thin enough to enhance the series microcrystalline film resistance.

Abstract: A lead frame that is suited for use on array types of integrated circuit packages to provide a high degree of compliance for absorbing mechanical stress induced by thermal changes includes a series of individual terminal elements that are connected in a strip form by means of break tabs disposed between adjacent elements. Each terminal element provides two spaced, generally parallel mounting surfaces that are resiliently connected to one another by means of an integral intermediate section. While the terminal elements are interconnected in strip form, one of the mounting surfaces of each element can be bonded to an associated attachment region on the semiconductor substrate. After all of the terminals of the strip have been so bonded, the break tabs between adjacent terminals can be removed to thereby separate the terminals from one another. The package which then results contains discrete compliant terminals which are suitable for subsequent surface attachment to the printed circuit board.

Abstract: An integrated circuit including CMOS transistors and an EPROM device by a method including selectively implanting threshold adjusting atoms of P-type in the channel regions of the N-type transistors while exposing the whole device area of the P-channel transistor. Subsequently, the sources and drains of the N-channel transistors are selectively implanted using the gates as a self-aligning mask portion. The PN-junction capacitance of the sources and drains of the N-channel transistors are thereby kept low and not subject to the degrading effects of the threshold adjusting implant. The P-channel is also affected and source drain capacitances there are reduced so that the speed of all three types of transistors are enhanced. Only high-yield process steps are included.

Abstract: A method of manufacturing a semiconductor device, in which a silicon slice (1) is locally provided with field oxide (10, 30) with a subjacent channel stopper zone (12, 32), which are formed during the same oxidizing heat treatment. The formed field oxide layer (10, 30) is removed in part by an etching treatment with a thinner and smaller field oxide layer (11, 31) being formed. The temperature at which the heat treatment is carried out is chosen so that lateral diffusion (15, 35) of the dopant forming the channel stopper zone (12, 32) extends in lateral direction practically over the same distance as the reduced field oxide layer (11, 31). Thus, it is achieved that, for example, for the manufacture of a MOS transistor an oxidation mask (7) having substantially the same width as a channel zone (17) to be formed can be used.

Abstract: A method for producing a semiconductor device comprises the steps of: forming an insulating layer on a semiconductor substrate provided with an electrode portion thereon, forming a barrier metal layer over the entire surface thereof, forming a groove in the barrier metal layer so that the groove surrounds the electrode portion, burying a stopper material in the groove, forming a bump on the barrier metal layer positioned on the electrode portion, and removing the barrier metal layer outside of the stopper. The stopper prevents the removal of the inside barrier metal layer during the removal of the outside barrier metal layer.

Abstract: A semiconductor device comprises a substrate, a semiconductor element mounted on the substrate, a cap having an opening smaller than the external size of the semiconductor element for covering the semiconductor element to provide a hermetic seal, and a heatsink member mounted on the cap to cover the opening and to make contact with the semiconductor element via the opening, so that heat generated by the semiconductor element is conducted directly to the heatsink member. A method of producing the semiconductor device comprises the steps of mounting the semiconductor element on the substrate, covering the semiconductor element by the cap which is fixed to the substrate, and mounting the heatsink member on the cap to cover the opening and to make contact with the semiconductor element via the opening.

Abstract: A method of manufacturing a compound semiconductor device has the steps of mirror-polishing a surface of each of two compound semiconductor substrates, bringing the mirror-polished surfaces of the two compound semiconductor substrates in contact with each other in a clean atmosphere and in a state wherein substantially no foreign substances are present therebetween, and annealing the compound semiconductor substrates which are in contact with each other so as to provide a bonded structure having a junction with excellent electrical characteristics at the interface.

Abstract: A single-level photoresist process is used to make metal-semiconductor field-effect transistors (MESFETs) having more uniform threshold voltages. An N.sup.- layer is formed in a semi-insulating semiconductor, followed by formation of a dummy gate using a single-level photoresist process. Using the dummy gate as a mask, ions are implanted to form an N.sup.+ region. The length of the dummy gate is then reduced by plasma etching. A dielectric is deposited over the N.sup.+ region, the N.sup.+ /N.sup.- interface, and the exposed portion of the N.sup.- layer. The dummy gate is lifted off to define a self-aligned, submicron gate opening. The gate opening on the N.sup.- layer is reactive ion etched to obtain the desired threshold voltage, and covered with a Schottky gate metal deposit.

Abstract: In the manufacture of integrated circuits, an undoped wide band-gap semiconductor is used for the insulating layer to isolate the silicon substrate from the metal interconnection pattern. To provide conductive vias through the insulating layer for connection to the source and drain of the transistors of the circuit, the wide band-gap semiconductor is implanted with a dopant selectively in the portion overlying the source and drain for making the implanted portion of low resistivity and of the conductivity type of the source and drain. Preferably, carbon is the wide band-gap semiconductor and nitrogen is the dopant implanted.

Abstract: An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metalization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.

Abstract: Power semiconductor devices are manufactured using a flexible metal tape carrier to facilitate automation of the manufacturing process. Control leads are fashioned from portions of the tape carrier, with a main portion of the tape carrier serving as a main current lead. The manufacturing process permits thorough electrical testing of a power semiconductor chip prior to incorporation into a relatively expensive power device package. In particular, the power chip can be tested at full-rated current, at least where the current is pulsed at a low duty cycle.

Abstract: A low collector parasitic resistance in bipolar transistors may be achieved without the use of an epitaxial layer or a high energy implant. Essentially, the invention employs the use of trenches in an N.sup.- layer overlying a P.sup.- substrate to surround the transistor, forming an N.sup.+ region in the walls defining the trench and below the surface, extending the trench into the P.sup.- substrate, implanting the bottom of the trench with a P-type dopant and refilling the trench with insulating material.The process of the invention permits fabrication of complex bipolar integrated circuits having a very high performance, and is particularly adaptable to very small geometry devices of 1 .mu.m and lower.

Abstract: An improved contact construction for an integrated circuit structure having closely spaced electrodes adjacent the contact is disclosed. The integrated circuit structure having the improved contact comprises a substrate having an insulating layer thereon, a first conductive layer over the insulating layer, and a second insulating layer formed over the first conductive layer. A self-aligned contact opening is formed through the second insulating layer, the underlying first conductive layer, and the first insulating layer to expose the substrate. A layer of insulating material is then formed on the sidewalls of the opening to cover the exposed edges of the first conductive layer. Conductive material is then placed in the self-aligned contact opening and a second conductive layer is formed over the second insulating layer whereby the conductive material placed in the self-aligned contact opening electrically connects the substrate with the second conducting layer.

Abstract: Grounding of source contacts (S) of flat devices and integrated circuits (of the FET type) is carried out according to the following process steps: a GaAs wafer is applied on a support and is covered on its free or rear face with photoresist; the latter is then etched along the border lines of the single FETs; the GaAs layer between contiguous FETs is removed also to make accessible the contacts S; a layer of noble metal is then deposited on the FET rear faces, so that it bridges the contacts S; the single metallized devices are disconnected from the initial support and finally are soldered to a package base.

Abstract: A method of forming a hermetic seal between two silicon wafers includes forming opposing troughs in each of the two wafers. In each trough are formed an isolation layer, a diffusion barrier and a tub of polysilicon. A gold strip is put on one polysilicon tub and the two silicon wafers are brought together and heated in a thermal gradient oven. A silicon gold eutectic is formed which migrates to the diffusion barrier of the silicon wafer.

Abstract: The fabrication of a layer of a III-V semiconductor material by vapor phase epitaxy is improved by precoating the walls of the deposition chamber in a suitable apparatus with the desired material. The coating of the deposition chamber is continued until the material being deposited is depth-uniform and of the same composition as the desired layer. Material then deposited on the substrate is free of depth compositional gradient. In a further improvement, the walls of the deposition chamber of the apparatus are roughened, thus providing nucleation sites for the growing coating and substantially reducing the time required to precoat the walls of the deposition chamber.

Abstract: A method of fabricating two terminal mesa semiconductor devices comprising etching a surface doped and metal coated silicon slice thereby to form a plurality of silicon frusta each capped by a metal contact pad, covering the frusta side of the slice with a metal contact continuity layer and then with a handle layer formed to lie parallel with that surface of the silicon slice which is remote from the frusta, lapping away the silicon slice to expose parts of the handle layer which extend between the frusta so that the frusta are separated so as to define discrete mesas held together by the handle layer, forming one of the two terminals on a face of the mesas remote from the contact pads, removing the handle layer to reveal the contact pads and bonding each contact pad thereby revealed to the metallized face of a diamond heat sink, one heat sink to each contact pad, which heat sink forms a part of the other of the two terminals of each mesa semiconductor device.