Abstract: In three-dimensional packaging of focal plane signal processing electroni the necessity of routing conductors from the face of the die to the edge of the die in the module for placement of inter-connection pads for interconnection to the next assembly presents the problem of electrical isolation of the conductors from adjacent silicon dies and their underlying silicon substrate. This problem is avoided by the use of a gold ribbon lead that is bonded to the face of each die. The ribbons function as electrically isolated conductive risers upon which inter-connection pads are placed for connection to the next assembly and as precision spacers between stacked dies during module assembly.

Abstract: A method for manufacturing a multichip package including the steps of forming a first polyimide insulating layer on a surface of a ceramic multilayer substrate having a circuit wiring therein, forming a first wiring connected to the circuit wiring of the multilayer substrate with a part of the first wiring being exposed at an open surface of the first polyimide insulating layer, forming a second polyimide insulating layer on a surface of a semiconductor element, and forming a second wiring connected with a circuit wiring of the semiconductor element in the second polyimide insulating layer with a part of the second wiring being exposed at an open surface of the second polyimide insulating layer.

Abstract: A simplified process for metal gate and contact/interconnect systems for MOS VLSI devices employs a refractory metal structure for the gate, including a thick layer of tungsten alone, with stress and adhesion controlled by the deposition conditions. The metal gate receives sidewall oxide spacers during a metal-cladding operation for the source/drain areas. Contacts to the source/drain region include a molybdenum/tungsten stack and a top layer of gold.

Abstract: A thin film etching process, wherein the rate of deposition of a robust sidewall passivant is controlled so that passivants can be continually deposited on the sidewalls of the resist pattern to change the geometry of the resist pattern during the processing step. That is, the existing pattern is modified as if a sidewall filament has been deposited on it, which can be advantageous for many purposes, without the added process complexity required by a sidewall filament process.

Abstract: A method of producing a cavity package semiconductor device is disclosed. The method includes providing a bar pad having a plurality of bar pad straps, each strap extending outwardly from the outer edge of the bar pad and spaced about the edge of the bar pad; mounting integrated circuits having bond pads on the bar pad; molding a packing material onto a central portion of lead fingers and the bar straps to grip and surround each lead finger with package material, with a portion of each lead finger extending externally from the ring at both the exterior and interior thereof and to secure the bar pad straps therein; electrically coupling the bond pads to the portion of desired ones of the lead fingers extending toward the interior of the ring; and enclosing both ends of the ring to provide a cavity in the ring to suspend a bar pad with the integrated circuit thereon within the cavity with the bar pad straps.

Abstract: A method for fabricating a Bi-CMOS device is disclosed herein, which device can include both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks.The device incorporates similar structural featues between the bi-polar and FET devices. The NPN and pFET can share the same well and a P+ diffusion (the p+ extrinsic base is the same as the p+ source). Also, the pnp and nFET can share the same well and an n+ diffusion.

Abstract: A method of manufacturing a semiconductor device includes the steps of (a) forming a first conductive pattern on a semiconductor substrate, (b) forming a first interlayer insulating film, covering the first conductive pattern, (c) forming a second conductive pattern, composed of a refractory metal, on the first interlayer insulating film, (d) forming a contact hole reaching the first conductive pattern through the second conductive pattern and the first interlayer insulating film at a predetermined position, (e) performing an annealing step before or after formation of the contact hole in step (d), and (f) covering in the contact hole with a metal film, after annealing step (e), to connect the second conductive pattern to the first conductive pattern. In this method, annealing step--for example, gettering--is performed before the wiring layer of the refractory metal is placed in contact with the semiconductor layer.

Abstract: For enhancement of device stability, there is disclosed a semiconductor device fabricated on a semiconductor substrate comprising (a) source and drain regions formed in a surface portion of the semiconductor substrate and spaced from each other by a channel region, (b) a gate insulating film formed on the channel region, (c) a gate electrode structure formed on the gate insulating film, and (d) a passivation film of an insulating material covering the gate electrode structure and containing hydrogen-bonded-silicons equal in number to or less than 5.times.10.sup.21 per cm.sup.3, and the unstable hydrogen-bonded-silicons are decreased in number so that the semiconductor device only have a decreased trap density which results in stable operation.

Abstract: A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self-aligned implantation is made possible by the process and structure using self-aligned etch. Programming of the memory cell uses standard EPROM programming, and erasing is accomplished by Fowler-Nordheim tunneling or photoemission. The memory cell can be made with a reduced cell size and read current uniformity is obtained.

Abstract: Two-terminal active devices, such as IMPATT and Gunn diodes, are combined with passive devices in a monolithic form using a plated metal heat sink to support the active elements and a coated-on dielectric to support the passive elements. Impedance-matching circuitry is preferably placed very close to (or partially overlapping) the active device, thereby eliminating detrimental device-to-circuit transition losses.

Abstract: A semiconductor device and associated method of fabrication in which the device includes a semiconductor substrate having a cavity therein extending in a frame pattern. An insulating layer such as one of silicon nitride is deposited in the cavity followed by the deposition of polysilicon to substantially fill the cavity and provide structural support. An epitaxy layer is formed over the surface of the substrate along with a second insulating layer having windows defined therein for enabling ohmic contact with the epitaxy layer and substrate, resectively. Metallization is deposited to form separate beam leads to provide ohmic contact at the epitaxy layer and substrate.

Abstract: The invention relates to the encapsulation of a seminconductor component in a plastic box.The fitting assembly comprises a radiator plate, a ceramic plate, a copper counter-electrode, a semiconductor pellet, a connecting pin with its end bent back and welded to the counter-electrode, whereby the latter is much larger than the pellet and occupies almost the entire surface of the ceramic plate. The ends of the other connecitng pins are bent back above the metallized zones of the upper pellet surface. Fiting takes place in a positioner machined in the form of successive cups with decreasing dimensions, in order to produce a welded stack having all the above elements, except the connecting pins, which are subsequently welded to the stack once the latter has been extracted from the positioner.

Abstract: A method of manufacturing an integrated circuit is set forth comprising a field effect transistor having an insulated gate (35) and a further circuit element having a first (9) and a second electrode zone (14) of opposite conductivity types. Simultaneously with the gate (35) a conductive pattern (11) separated by an insulating layer (34) from the first electrode zone (9) is provided on the first electrode zone (9). This pattern (11) provides a pair of the edge of the doping opening (12) for the second electrode zone (14). A second insulating layer (16) is provided on the pattern (11) and is removed locally by anisotropic etching in such a manner that in the doping opening (12) edge portions (17) (16) are left. Subsequently, a conductive layer (22) for connection of the second electrode zone (14) is provided, which extends over the second insulating layer (16), over the pattern (11) and over the edge portions (17) (16 ) into the opening (12) of reduced size and on the second electrode zone (14).

Abstract: A lead frame and method for processing the lead frames from a continuous strip of lead frames. A first insulation support member and a second insulative support member are first molded to the lead frame. After the support members are formed, the positioning member for supporting the leads within the lead frame is stamped from the lead frame. After an integrated circuit (IC) is connected to the leads, the IC can be tested within the lead frame since the leads are electrically isolated from the lead frame and each other. Finally the IC can be encapsulated and the leads severed from the lead frame assembly.

Abstract: To encapsulate integrated circuits mounted on continuous dielectrical strips (surface-mounted circuits) it is proposed to transfer mold a thermosetting resin around circuits carried by the strip, the resin being injected outside the parting plane of the mold, contrary to the usual practice in this field. The protection of the circuits is improved while, at the same time, the ability to test the strip is preserved.

Abstract: A support is formed and comprises a base, a resin layer which is formed on the base and on recesses which are formed on a surface of the base, and a conductive layer which is formed on a portion of a surface of the resin layer, other than where the recesses are formed. The surface of the recesses is electrically charged by way of a corona discharge to create static electricity in the recesses. Metal balls to be formed into bump electrodes are held in the recesses by way of the static electricity. Then, each of the metal balls is bonded to a corresponding electrode terminal of an electronic component by hot press unit while the electronic component is opposed to the support.

Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region.

Abstract: A novel process and structure is taught which provides discrete semiconductor islands located in a semiconductor substrate, the islands being electrically isolated from each other. Certain of these islands, in addition to being electrically isolated from other islands, are also electrically isolated from the substrate. Yet other ones of these islands are electrically isolated from other islands, but are electrically connected to the substrate. In accordance with the teachings of this invention, a substrate is used and a layer of electrical insulation is formed over only a portion of the surface of the substrate. Grooves are then formed to serve as vertical isolation regions. The grooves are filled with a non-conductive material, or covered with a layer of insulation on their sides and bottom, and filled with any convenient material, such as polycrystalline silicon. A second semiconductor substrate is then bonded to the first, and serves as the ultimate substrate of the finished device.

Abstract: Low defect density oxides suitable for use as thin gate oxides or in charge storage capacitors are described. First and second layers are formed on a substrate with misaligned defect structures. A third layer is then grown by diffusing a species through the first and second layers to the substrate. The species reacts with the substrate. The low defect density results from the misaligned defect structure of the first and second layers. In one embodiment, the first and second layers are grown and deposited oxides, respectively. The third layer is grown by diffusing oxygen through the first two layers and the interface between the first and second layers acts as a sink trapping defects. The oxide silicon interface has desirable characteristics because the oxide grows in near equilibrium conditions.

Abstract: Process and apparatus employing flame ashing for stripping photoresist from a substrate in the manufacture of a semiconductor device. The substrate is exposed to the flame with the photoresist to be removed being contacted directly by the flame to oxidize, or ash, the photoresist. The flame is produced by burning oxygen and a gaseous fuel, and the rate of ashing is increased by preheating the substrate. Nitrogen, a nitrogen-containing gas or an inert gas is added to the fuel to provide a cooler flame and an improved ashing rate. In one disclosed embodiment, the oxygen and the gaseous fuel are discharged through a plurality of spaced apart openings in a burner and the substrate is moved relative to the frames to successively ash different portions of the photoresist.