Abstract: A method of fabricating a semiconductor device which includes:(1) a step of forming an opening in a silicon substrate using a first silicon oxide film and a first silicon nitride film formed on the silicon substrate as masks,(2) a step of forming a second silicon oxide film and a second silicon nitride film on the side wall of the opening by the reduced pressure CVD method and anisotropic etching method,(3) a step of performing isotropic dry etching using the first and second silicon oxide films as masks, and(4) a step of performing heat treatment in an oxidizing atmosphere using the first and second silicon nitride films as masks.Thereby, uniform isotropic etching may be accomplished by use of the dry etching method.

Abstract: In accordance with the teachings of this invention, resistors are fabricated in semiconductor devices utilizing a layer of semiconductor material having a preselected resistivity. Means are provided for electrically isolating the semiconductor region from the regions located beneath, and isolation to adjacent regions is provided by forming a groove. Resistance value of a particular resistor fabricated in accordance with the teachings of this invention is dependent, in a coarse fashion, on the length and width of the resistor, as well as the resistivity of the semiconductor material used to fabricate the resistor. However, the final resistance value is determined by the diffusion of high concentration isolation dopants which serve to accurately control the effective cross-sectional area of the resistor.

Abstract: A method of encapsulating an electronic device on a substrate comprises depositing a radiatively curable barrier wall to contain a subsequently deposited encapsulant. Alternatively, an encapsulant comprising a majority of radiatively curable material is used in the absence of a barrier wall.

Abstract: A system of establishing a conductive via path between spaced interlevel conductors. Successive layers of metallization separated by a dielectric are built. The vias are opened in one step to eliminate interlevel mashing. The system employs annular pads at locations where contact may be established to another wiring level. The vias are self-aligned and taper from top metal to first level contact. The system is applicable both chip-wise and carrier-wise.

Abstract: A multichip package comprises a multilayer wiring substrate, and an array of contact pads having the ability to make wiring change formed on an uppermost layer of the substrate. The multichip package further comprises a plurality of IC chips mounted on the substrate. Each contact pad includes a connection conductor portion, and a separable conductive portion connecting a chip to an internal conductive layer provided in the substrate and integrally joined to the connection conductor portion. A connection is deleted by cutting the separable conductive portion thereafter to connect a wire to the connection conductor for making a wiring change, thus realizing the multichip package provided with an engineering change contact pad having excellent connecting and cutting functions.

Abstract: An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

Abstract: A semiconductor device which comprises: a first main electrode on a first main surface of the semiconductor substrate, and a second main electrode on a second main surface thereof, the first main surface including a control electrode; a first outer main electrode and a second outer main electrode provided on the first and second main surface, respectively, wherein the first and second outer main electrodes are respectively connected to the first main electrode and the second main electrode; an external control electrode adapted for connection to the control electrode on the semiconductor substrate; a control electrode access electrode whereby the control electrode on the substrate is connected to the external control electrode; the control electrode access electrode including a ring-shaped body having a contact section on the undersurface thereof, and a lead for connection to the external control electrode, wherein the ring-shaped body is covered with an insulating film in the portion excluding the contact se

Abstract: A multi-layered molded plastic package for encapsulating an integrated circuit is described. The package includes a carrier having a double-layered metal plate which are separated by an adhesive coated insulation tape. A second insulating tape layer is used to bond externally extending leads onto one of the metal plates. Power and ground connections from the terminal of the integrated circuit are made to each of the plates, respectively, as are the power and ground lead connections to the two plates. The power and ground planes remove the requirement for direct physical connection between the power and ground terminals of the integrated circuit and their respective leads.

Abstract: A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by solder. The metallized ceramic lid is sealed to the metallization ring on the sidebrazed ceramic body by means of the conventional gold-tin solder. The resultant hermetic seal can be inspected by observing the solder fillet in the lid recess. Such a closure seal is fully hermetic and can readily survive repeated thermal cycling.

Abstract: A method of manufacturing hermetically sealed circuit assemblies (10) having circuit elements (74, 76, 78 and 80) to be compression bonded, a hermetically sealed circuit assembly having circuit elements to be compression bonded and a stack containing at least one hermetically sealed circuit assembly having circuit elements which are compression bonded is disclosed. Uniform thickness of individual hermetically sealed circuit assemblies measured across columns (22-30) is insured by positioning deformable spacers (124-132) in the columns containing the circuit elements to be compression bonded, and deforming the deformable spacers so that a surface of each of the deformed spacers lies within a single plane. Thereafter a compressive force is applied to a stack of one or more circuits through the columns which contain the circuit elements to be compression bonded.

Abstract: An image sensor array and method of fabrication which facilitates replacement of a defective one in a series of arrays butted together to form a longer scanning array in which a (110) silicon wafer having a row of photosites has separation lines etched thereon by orientation dependent etching along the (111) planes, with the separation lines for the opposite ends of the array each consisting of first and second partial boundary lines longitudinally offset from one another connected by a third boundary line so that the ends of the array have a has a generally L-shaped offset permitting bi-directional separating and aligned inserting movement when replacing a defective array.In a second embodiment, the arrays are formed on (100) silicon with alternating `nail` head and `mesa` head shapes to facilitate removal and replacement of a defective array.

Abstract: A PRIMOS (Planar Recessed Isolated MOS) transistor and a method for fabricating same is described wherein the source and drain in a semiconductor body are separated by a recess. A gate oxide is disposed on the body in the recess, with conductive gate material thereon. Oxide regions are positioned on each side of the gate, such oxide regions being substantially thicker in cross-section than the gate oxide. The method described teaches fabrication of this device.

Abstract: Metal contacts and interconnections for semiconductor integrated circuits are fabricated through the deposition of a sandwich structure of metal. The bottom layer of a refractory metal prevents aluminum spiking into silicon; the top layer of refractory metal or alloy serves to reduce hillocking of the middle layer of conductive material. The upper layer of refractory metal at the location of the contact pads is etched off to improve bonding during packaging.

Abstract: A lead frame for use with an integrated circuit chip comprises a plurality of lead frame segments, each segment comprising a plurality of leads the inner ends of which converge towards a pad area for the chip encircled by the segments.

Abstract: The invention is a semiconductor device assembly and method of making the same. A mounting plate has positioning means for positioning the plate relative to a header, a first mounting surface of the plate is attached to the header and a semiconductor device is attached to a second mounting surface of the mounting plate. The assembly is made by forming the mounting plate, positioning the mounting plate relative to the header by the positioning means, attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. Another method of making the assembly is by defining and etching a mounting plate and attaching the first mounting surface to the header and the semiconductor device to the second mounting surface. This assembly and process provides an efficient means for mounting semiconductor devices and in particular electro-optic devices such as lasers.

Abstract: A method of rapid thermal annealing a wafer of an ion implanted III-V compound semiconductor material by heating the wafer in close proximity to a III-V compound semiconductor wafer coated with a layer of tin or indium. A localized overpressure of the Group V element is produced by the combination of the III and V elements with the tin or indium tending to reduce surface decomposition of the implanted wafer.

Abstract: A direct moat wafer processing for maximizing the functional continuity of a field oxide layer employs a processing sequence through which respective differently sized apertures are successively formed in the oxide layer. A first of these apertures prescribes the size of the polysilicon gate, while a second aperture is formed around the completed gate structure and prescribes the geometry of source/drain regions to be introduced into exposed surface areas of the substrate on either side of the gate. The sidewalls of the first and subsequently formed, second aperture are effectively perpendicular to the substrate surface, thereby maintaining the functional continuity of the field oxide layer across the entirety thereof. Thereafter, a separate gate interconnect layer is selectively formed atop the field oxide layer to provide a conductive path to the gate.

Abstract: A method for making a semiconductor device of a type comprising at least first and second semiconductor circuit units, which method comprises the step of forming a plurality of connecting electrodes on an upper surface of each of at least first and second semiconductor substrates; forming an electrically insulating layer entirely over the upper surface of each of the first and second substrates so as to cover the respective connecting electrodes; partially removing the insulating layer on each of the first and second substrates to permit the respective electrodes to be exposed to the outside; forming metal studs on the first substrate in contact with the electrodes so as to protrude outwardly of the respective insulating layer to complete the first semiconductor unit and forming solder deposits on the second substrate in contact with the respective electrodes on such second substrate to complete the second semiconductor unit; combining the first and second semiconductor units with the metal studs in the first

Abstract: A method for generating a strip laser in a buried hetero-structure composed of layers, wherein a raised strip is etched out of the layer structure and the strip is laterally etched with an erosion melt. The lateral edges of the laser active layer are protected by leaving them covered with a portion of the layer dissolved out by the erosion melt. The deposits thus remaining are used to initiate the generation of an epitaxial layer which extends laterally from the laser-active layer.

Abstract: A method of making semiconductive developments, especially MESFETs, which applies a template to a surface of the substrate previously formed with circuit elements in alignment with these elements and so bonds the template to the substrate that the template can be utilized as a holder for the substrate. The rear surface is then coated with a resist and a second template aligned externally with the first utilizing markings exterior to the substrate to form the structure on the rear surface which can include throughholes for a metal deposit extending through the preferably GaAs substrate.