Patents Examined by Bitew Dinke
  • Patent number: 10463433
    Abstract: A system for surgical planning and assessment of spinal deformity correction is provided that has a spinal imaging system and a control unit. The spinal imaging system is configured to collect at least one digitized position of one or more vertebral bodies of a subject. The control unit is configured to receive the at least one digitized position, and calculate, based on the at least one digitized position, an optimized posture for the subject. The control unit is configured to receive one or more simulated spinal correction inputs, and based on the inputs and optimized posture, predict an optimal simulated postoperative surgical correction.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: November 5, 2019
    Assignee: NuVasive, Inc.
    Inventors: Alex Turner, Jeffrey Harris
  • Patent number: 10461387
    Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assist in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assist in impedance matching.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: October 29, 2019
    Assignee: Aviat U.S., Inc.
    Inventors: Jayesh Nath, Ying Shen
  • Patent number: 10446485
    Abstract: A semiconductor device includes: a plurality of first wires formed in a first layer and indicating fixed potentials; and an inductor formed in a second layer stacked on the first layer, and wiring widths of the first wires located within a range of a formation region of the inductor in a plan view among the plurality of first wires are formed narrower than wiring widths of the first wires located outside the range of the formation region of the inductor.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 15, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shinichi Uchida
  • Patent number: 10424477
    Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: September 24, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Antti J. Niskanen, Shang Chen, Viljami Pore
  • Patent number: 10411120
    Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the cha
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
  • Patent number: 10400509
    Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artificial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 3, 2019
    Assignee: King Fahd University of Petroleum and Minerals
    Inventors: Mohammed Abdul Fasi, Ismail Mohammad Budaiwi
  • Patent number: 10396154
    Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10395917
    Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 27, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Antti J. Niskanen, Shang Chen, Viljami Pore, Atsuki Fukazawa, Hideaki Fukuda, Suvi P. Haukka
  • Patent number: 10388644
    Abstract: A method of manufacturing conductors for a semiconductor device, the method comprising: forming a structure on a base; and eliminating selected portions of members of a first set and selected portions of members of a second set from the structure. The structure includes: capped first conductors arranged parallel to a first direction; and capped second conductors arranged parallel to and interspersed with the capped first conductors. The capped first conductors are organized into at least first and second sets. Each member of the first set has a first cap with a first etch sensitivity. Each member of the second set has a second cap with a second etch sensitivity. Each of the capped second conductors has a third etch sensitivity. The first, second and third etch sensitivities are different.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Hui-Ting Yang, Ko-Bin Kao, Ru-Gun Liu, Shun Li Chen
  • Patent number: 10383572
    Abstract: A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on a bottom surface of the substrate, patterning the first photoresist layer and the second photoresist layer to remove at least a first portion of the first photoresist layer and at least a second portion of the second photoresist layer, filling the one or more vias, the first portion and the second portion with solder material using injection molded soldering, and removing remaining portions of the first photoresist layer and the second photoresist layer.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Shriya Kumar, Jae-Woong Nah
  • Patent number: 10381475
    Abstract: A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Andreas Meiser, Karl-Heinz Gebhardt, Till Schloesser, Detlef Weber
  • Patent number: 10374163
    Abstract: A field effect transistor includes a carbon nanotube layer formed adjacent to a gate structure. Two intermetallic contacts are formed on the carbon nanotube layer. The two intermetallic contacts include an oxidation resistant compound having a work function below about 4.4 electron-volts.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matthew W. Copel, Damon B. Farmer, Talia S. Gershon, Paul M. Solomon
  • Patent number: 10367025
    Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 30, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yoshihiro Sato, Ryohei Miyagawa, Tokuhiko Tamaki, Junji Hirase, Yoshiyuki Ohmori, Yoshiyuki Matsunaga
  • Patent number: 10367031
    Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 30, 2019
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Anne Vandooren, Nadine Collaert
  • Patent number: 10358869
    Abstract: A control system is disclosed that includes a room controller transmitting signals to both a shade control network and a light control network, directing that motorized roller shades and dimmable lights be set to desired intensity levels. The control system further includes an intelligent hub that provides a trickle-charge re-charge current via power-over-Ethernet cables to batteries associated with each of the motorized roller shades for re-charging the batteries, thereby eliminating power supplies being installed within walls. The intelligent hub provides for communication with the room controller based on streaming protocol and with the shade control network based on event-based protocol. A computer running user interface software may be connected to the system to facilitate programming.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: July 23, 2019
    Assignee: Crestron Electronics, Inc.
    Inventor: George Feldstein
  • Patent number: 10347755
    Abstract: Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 1×106 ?·cm or more, a channel layer located on the base layer, being a GaN layer having a total impurity density of 1×1017/cm3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition AlxInyGa1-x-yN (0?x?1, 0?y?1).
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 9, 2019
    Assignee: NGK INSULATORS, LTD.
    Inventors: Yoshitaka Kuraoka, Mikiya Ichimura, Makoto Iwai
  • Patent number: 10338551
    Abstract: A computer-implemented method for automatically exchanging data between a piping and instrumentation diagram (P&ID) and a control system comprises: parsing a P&ID and identifying instruments and/or groups of instruments within the P&ID, identifying one or more input tags and output tags associated with each identified instrument and/or with each identified group of instruments within the P&ID, and establishing at least one relationship among the one or more input tags and output tags, wherein the input tags and output tags for an instrument and/or a group of instruments and the at least one relationship between the corresponding input tags and output tags are derivable from a template library, and identifying a control loop for each established relationship among the input tags and the output tags, wherein said control loop is for controlling one or more instruments by the control system.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: July 2, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Václav Jirkovský, Marek Obitko, Robert Mavrov, Alexander B. Cherpakov, Anthony C. Barrancotta
  • Patent number: 10332959
    Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
  • Patent number: 10329839
    Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artifcial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: June 25, 2019
    Assignee: King Fahd University of Petroleum and Minerals
    Inventors: Mohammed Abdul Fasi, Ismail Mohammad Budaiwi
  • Patent number: 10329838
    Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artificial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 25, 2019
    Assignee: King Fahd University of Petroleum and Minerals
    Inventors: Mohammed Abdul Fasi, Ismail Mohammad Budaiwi