Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

Abstract: A field effect transistor includes a carbon nanotube layer formed adjacent to a gate structure. Two intermetallic contacts are formed on the carbon nanotube layer. The two intermetallic contacts include an oxidation resistant compound having a work function below about 4.4 electron-volts.

Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

Abstract: In a method of manufacturing a semiconductor device, a first contact hole is formed in one or more dielectric layers disposed over a source/drain region or a gate electrode. An adhesive layer is formed in the first contact hole. A first metal layer is formed on the adhesive layer in the first contact hole. A silicide layer is formed on an upper surface of the first metal layer. The silicide layer includes a same metal element as the first metal layer.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.

Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

Abstract: A method includes forming one or more vias in a substrate, forming at least one liner on at least one sidewall of at least one of the vias, and filling said at least one via with solder material using injection molded soldering. The at least one liner may comprise a solder adhesion layer, a barrier layer, or a combination of a barrier layer and a solder adhesion layer.

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.

Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.

Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings. Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.

Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.

Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

Abstract: Semiconductor structure and fabrication method thereof are provided. An exemplary method includes providing a semiconductor substrate including a plurality of first fin structures, each having a first width, and a plurality of second fin structures, each having a second width greater than the first width. The method further includes forming a first isolation film covering sidewall surfaces of the first fin structures and the second fin structures, forming a trench in the first isolation film to expose at least a top portion of at least one sidewall surface of one or more second fin structures, forming an isolation fluid layer to fill the trenches, and performing an oxygen annealing process to convert a surface layer of the top portion of the at least one sidewall surface of the one or more second fin structures into a by-product layer, and to convert the isolation fluid layer into a second isolation film.

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

Abstract: A semiconductor device comprises: a gate insulating film 190 stacked on a semiconductor layer 130; and a gate electrode layer 230 stacked on the gate insulating film 190 and provided to apply a voltage via the gate insulating film 190 for formation of a channel in the semiconductor layer 130. The gate insulating film 190 includes: a first insulation film 192 stacked on the semiconductor layer 130; and a second insulation film 194 between the first insulation film 192 and the gate electrode layer 230. When ?1 and ?2 respectively represent relative permittivities of the first and second insulation film 192, 194, d1 [nm] and d2 [nm] represent film thicknesses of the first and second insulation film 192, 194, and Vmax [V] represents a rated voltage applicable to the gate electrode layer 230, the semiconductor device is configured to satisfy ?1<?2 and meet (C1): V ? max d ? ? 1 + ? ? ? 1 ? ? ? 2 · d ? ? 2 ? 21 ? [ MV ? / ? cm ] .

Abstract: Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.

Abstract: A smart window controller includes circuitry configured to establish a representative model of one or more building zones based on occupancy, construction, lighting, or cooling properties of a building. A lighting control strategy is implemented for the one or more building zones based on the representative model or one or more user preferences input at a first user interface screen of an external device. Automatic operations of one or more smart windows, cooling systems, or artificial lighting systems are controlled based on trigger points associated with the lighting control strategy, and a performance level of the lighting control strategy for the one or more building zones is determined based on one or more predetermined financial metrics.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at leas