Patents Examined by Bitew Dinke
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Patent number: 11588062Abstract: Structures for a photodetector and methods of fabricating a structure for a photodetector. A photodetector includes a photodetector pad coupled to a waveguide core and a light-absorbing layer coupled to the photodetector pad. The light-absorbing layer has a body, a first taper that projects laterally from the body toward the waveguide core, and a second taper that projects laterally from the body toward the waveguide core. The photodetector pad includes a tapered section that is laterally positioned between the first taper and the second taper of the light-absorbing layer.Type: GrantFiled: October 8, 2020Date of Patent: February 21, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Abdelsalam Aboketaf, Yusheng Bian
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Patent number: 11587783Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).Type: GrantFiled: November 23, 2020Date of Patent: February 21, 2023Assignee: ASM IP HOLDING B.V.Inventors: Antti J. Niskanen, Shang Chen, Viljami Pore, Atsuki Fukazawa, Hideaki Fukuda, Suvi P. Haukka
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Patent number: 11576727Abstract: A system for surgical planning and assessment of spinal deformity correction is provided that has a spinal imaging system and a control unit. The spinal imaging system is configured to collect at least one digitized position of one or more vertebral bodies of a subject. The control unit is configured to receive the at least one digitized position, and calculate, based on the at least one digitized position, an optimized posture for the subject. The control unit is configured to receive one or more simulated spinal correction inputs, and based on the inputs and optimized posture, predict an optimal simulated postoperative surgical correction.Type: GrantFiled: March 19, 2021Date of Patent: February 14, 2023Assignee: NuVasive, Inc.Inventors: Alex Turner, Jeffrey Harris
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Patent number: 11574887Abstract: A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.Type: GrantFiled: March 24, 2020Date of Patent: February 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: James Fred Salzman
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Patent number: 11569362Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.Type: GrantFiled: July 13, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ming Hsu, Pei-Yu Chou, Chih-Pin Tsao, Kuang-Yuan Hsu, Jyh-Huei Chen
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Patent number: 11563106Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.Type: GrantFiled: April 27, 2020Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11562953Abstract: An integrated circuit includes two parallel active zones extending in a first direction, an n-type pick-up region, and a p-type pick-up region. The two parallel active zones includes a p-type active zone located in an n-type well and an n-type active zone located in a p-type well. The n-type pick-up region is located in the n-type well and configured to have a first supply voltage. The p-type pick-up region is located in the p-type well and configured to have a second supply voltage, wherein the second supply voltage is lower than the first supply voltage. The n-type pick-up region and the p-type pick-up region are separated from each other along a direction that is different from the first direction.Type: GrantFiled: October 22, 2019Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Hui Chen, Hao-Chieh Chan
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Patent number: 11557745Abstract: To provide a method for manufacturing a lightweight light-emitting device having a light-emitting region on a curved surface. The light-emitting region is provided on a curved surface in such a manner that a light-emitting element is formed on a flexible substrate supported in a plate-like shape and the flexible substrate deforms or returns.Type: GrantFiled: December 4, 2020Date of Patent: January 17, 2023Inventors: Yoshiharu Hirakata, Shunpei Yamazaki
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Patent number: 11552136Abstract: An electronic apparatus includes: an electronic panel comprising a display unit comprising a plurality of pixels and a sensing unit comprising a plurality of sensing electrodes; and an electronic module overlapping with the electronic panel when viewed in a plan view, the sensing unit comprising: a base substrate comprising a hole area overlapping with the electronic module, an active area overlapping with the sensing electrodes, and a peripheral area adjacent to the active area; a connection line in the hole area and connected to a portion of the sensing electrodes; and a conductive light blocking pattern in the hole area and spaced apart from the connection line and the sensing electrodes.Type: GrantFiled: April 9, 2020Date of Patent: January 10, 2023Assignee: Samsung Display Co., Ltd.Inventors: Il-Joo Kim, Wonkyu Kwak, Jinsuk Lee, Chung Yi, Sungho Cho
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Patent number: 11539022Abstract: To provide a method for manufacturing a lightweight light-emitting device having a light-emitting region on a curved surface. The light-emitting region is provided on a curved surface in such a manner that a light-emitting element is formed on a flexible substrate supported in a plate-like shape and the flexible substrate deforms or returns.Type: GrantFiled: December 4, 2020Date of Patent: December 27, 2022Inventors: Yoshiharu Hirakata, Shunpei Yamazaki
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Patent number: 11532748Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.Type: GrantFiled: September 28, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
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Patent number: 11527526Abstract: The present disclosure provides a semiconductor device manufacturing method. The method includes: providing a semiconductor substrate, including a high-frequency-block group and a low-power-block group; forming high-frequency-type logic standard cells on the high-frequency-block group of the semiconductor substrate. The high-frequency-type logic standard cells have a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power. The method further includes forming low-power-type logic standard cells on the low-power-block group of the semiconductor substrate. The low-power-type logic standard cells have a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power.Type: GrantFiled: October 1, 2020Date of Patent: December 13, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) CorporationInventors: Xin Gui Zhang, Yao Qi Dong
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Patent number: 11522079Abstract: An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.Type: GrantFiled: October 16, 2019Date of Patent: December 6, 2022Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Victor Kairys, Ruth Shima-edelstein
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Patent number: 11515157Abstract: A method for fabricating a capacitor includes forming a first electrode, forming a dielectric layer stack on the first electrode, the dielectric layer stack including an initial hafnium oxide layer and a seed layer having a doping layer embedded therein, forming a thermal source layer on the dielectric layer stack to crystallize the initial hafnium oxide into tetragonal hafnium oxide, and forming a second electrode on the thermal source layer.Type: GrantFiled: November 13, 2019Date of Patent: November 29, 2022Assignee: SK hynix Inc.Inventors: Se-Hun Kang, Yu-Jin Kim, Deok-Sin Kil
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Patent number: 11515220Abstract: A semiconductor package structure includes a carrier, an electronic device, a spacer, a transparent panel, and a conductive wire. The electronic device has a first surface and an optical structure on the first surface. The spacer is disposed on the first surface to enclose the optical structure of the electronic device. The transparent panel is disposed on the spacer. The conductive wire electrically connects the electronic device to the carrier and is exposed to air.Type: GrantFiled: December 4, 2019Date of Patent: November 29, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia Yun Hsu, Ying-Chung Chen
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Patent number: 11515437Abstract: A light sensor includes a photodiode, interlayer dielectric layer and plurality of metal layers. A polarizer is disposed in the plurality of metal layers. The photodiode is coupled to generate charge in response to incident light directed through a first side of the semiconductor layer. The polarizer includes a first metal grid formed with a first metal layer and a second metal grid formed with a third metal layer. The second metal grid is stacked with the first metal grid such that the first and second metal grids are disposed above and aligned with the photodiode. The photodiode is optically coupled to receive incident light through the first and second metal grids of the polarizer and through the first side of the semiconductor layer.Type: GrantFiled: December 4, 2019Date of Patent: November 29, 2022Assignee: OmniVision Technologies, Inc.Inventors: Alireza Bonakdar, Shinn-Jhy Lian
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Patent number: 11508870Abstract: The invention relates to a process for fabricating at least tensilely strained planar photodiode 1, comprising producing a stack formed from a semiconductor layer 53, 55 made of a first material and from an antireflection layer 20; producing a peripheral trench 30 that opens onto a seed sublayer 22 made of a second material of the antireflection layer 20; epitaxy of a peripheral section 31 made of the second material in the peripheral trench 30; and returning to room temperature, a detecting section 10 then being tensilely strained because of the difference in coefficients of thermal expansion between the two materials.Type: GrantFiled: October 8, 2020Date of Patent: November 22, 2022Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Abdelkader Aliane, Jean-Louis Ouvrier-Buffet
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Patent number: 11495540Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.Type: GrantFiled: October 22, 2019Date of Patent: November 8, 2022Assignee: Tokyo Electron LimitedInventors: Lars Liebmann, Jeffrey Smith, Anton deVilliers
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Patent number: 11482460Abstract: A semiconductor package structure includes a carrier, an electronic device, a spacer, a transparent panel, and a conductive wire. The electronic device has a first surface and an optical structure on the first surface. The spacer is disposed on the first surface to enclose the optical structure of the electronic device. The transparent panel is disposed on the spacer. The conductive wire electrically connects the electronic device to the carrier and is exposed to air.Type: GrantFiled: December 4, 2019Date of Patent: October 25, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia Yun Hsu, Ying-Chung Chen
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Patent number: 11469215Abstract: A chip package structure is provided. The chip package structure includes a wiring structure. The chip package structure includes a first chip structure over the wiring structure. The chip package structure includes a first molding layer surrounding the first chip structure. The chip package structure includes a second chip structure over the first chip structure and the first molding layer. The chip package structure includes a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The chip package structure includes a third chip structure over the second chip structure and the second molding layer. The chip package structure includes a third molding layer surrounding the third chip structure and over the second chip structure and the second molding layer. The chip package structure includes a fourth molding layer surrounding the second molding layer and the third molding layer.Type: GrantFiled: February 26, 2020Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yu Chen, An-Jhih Su