Abstract: There is provided a solar panel including: solar cells each of which is formed in a belt-shape extending in a predetermined direction on a plate-shaped surface and which are disposed in rows in a cell-width direction; a partition area that divides the solar cells from each other; and a connecting part that connects adjoining solar cells among the solar cells electrically in series at respective ends in the extending direction. The solar cells have, across at least two of the solar cells, a transparent power generation area in which a power generation area and a transparent area are alternately disposed in the extending direction. The transparent power generation area extends over an entire cell width of at least one of the solar cells, and the connecting part is disposed at each of opposite ends in the extending direction of the at least one solar cell.

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

Abstract: A system includes an image sensor structure and a flow cell. The image sensor structure includes an image layer disposed over a base substrate. A device stack is disposed over the image layer. A bond pad is disposed in the device stack. A passivation stack is disposed over the device stack and the bond pad. An array of nanowells is disposed in a top layer of the passivation stack. A through-silicon via (TSV) is in electrical contact with the bond pad. The TSV extends through the base substrate. A redistribution layer (RDL) is disposed on a bottom surface of the base substrate. The RDL is in electrical contact with the TSV. The flow cell is disposed upon the top layer of the passivation stack to form a flow channel therebetween. The flow channel is disposed over the array of nanowells and the bond pad.

Abstract: A sensor includes a first electrode, a second electrode facing the first electrode, and a light absorbing layer between the first electrode and the second electrode. The light absorbing layer may have a first absorption spectrum having a first absorption peak in a first infrared wavelength region and a second absorption peak in a second infrared wavelength region, the second infrared wavelength region being a longer wavelength region than the first infrared wavelength region. The second absorption spectrum does not at least partially overlap with the first absorption spectrum. The second absorption spectrum may have a lower absorption intensity than the first absorption spectrum. An external quantum efficiency (EQE) spectrum that is amplified in the second infrared wavelength region is exhibited in the sensor.

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes a carrier conducting layer having a first surface; an absorption region is doped with a first dopant having a first conductivity type and a first peak doping concentration, wherein the carrier conducting layer is doped with a second dopant having a second conductivity type and a second peak doping concentration, wherein the carrier conducting layer comprises a material different from a material of the absorption region, wherein the carrier conducting layer is in contact with the absorption region to form at least one heterointerface, wherein a ratio between the first peak doping concentration of the absorption region and the second peak doping concentration of the carrier conducting layer is equal to or greater than 10; and a first electrode and a second electrode both formed over the first surface of the carrier conducting layer.

Abstract: A solid-state imaging element including a photoelectric conversion layer of a first electrical conductivity type including a plurality of pixel regions, an electrode electrically coupled to the photoelectric conversion layer and provided for each of the pixel regions, a semiconductor layer provided between the electrode and the photoelectric conversion layer and having a bandgap larger than a bandgap of the photoelectric conversion layer, a diffusion part disposed in a vicinity of an edge of the pixel region and including an impurity of a second electrical conductivity type that is diffused from the semiconductor layer across the photoelectric conversion layer, and a non-diffusion part provided inside the diffusion part and not including the impurity of the second electrical conductivity type in the photoelectric conversion layer.

Abstract: A substrate processing apparatus according to an aspect of the present disclosure includes a mounting section on which a substrate is placed, a structure member provided above the mounting section so as to face the mounting section, and an optical sensor. The optical sensor is configured to detect a height of the mounting section, a height of the structure member, and a height of the substrate, by emitting light from above the structure member to a predetermined location of the mounting section, a predetermined location of the structure member, and the substrate, and by receiving reflection light from the mounting section, the structure member, and the substrate.

Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The chip package structure includes a first molding layer surrounding the first chip and the second chip. The first molding layer is a single layer structure. A first boundary surface between the passivation layer and the second molding layer extends toward the first chip. The chip package structure includes a second molding layer surrounding the third chip and the first molding layer. A first bottom surface of the first molding layer and a second bottom surface of the second molding layer are substantially coplanar.

Abstract: An imaging device includes a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked. A semiconductor material layer including an inorganic oxide semiconductor material having an amorphous structure at least in a portion is formed between the first electrode and the photoelectric conversion layer, and the formation energy of an inorganic oxide semiconductor material that has the same composition as the inorganic oxide semiconductor material having an amorphous structure and has a crystalline structure has a positive value.

Abstract: A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Abstract: A color separation element and an image sensor including the same are disclosed. The color separation element includes a spacer layer, and a color separation lens array including at least one nano-post provided in the spacer layer to control a phase distribution of incident light so that light having the same wavelength of the incident light is multi-focused on a plurality of target regions; and periodic regions in which the phase distribution control layer is repeatedly arranged.

Abstract: A method for calibrating a second bonding machine based on a calibrated first bonding machine is disclosed. The first bonding machine includes a first ultrasonic transducer. The second bonding machine includes a second ultrasonic transducer and a power supply. The method includes providing a first electrical calibration supply that causes the first ultrasonic transducer to oscillate at a first calibration amplitude when it is damped by a mechanical damping, providing a second electrical calibration supply that causes the second ultrasonic transducer to oscillate at the same calibration amplitude when it is damped by the same mechanical damping.

Abstract: A household appliance includes a housing; a treating chamber located within the housing and having an access opening; a closure element movable relative to the access opening between opened and closed positions to selectively provide access to the treating chamber through the access opening; a controller associated with the housing and implementing a treating cycle on at least one item in the treating chamber; and a human-machine interface. The HMI includes a first portion associated with the housing and a second portion associated with the closure element. The first portion includes non-touch sensitive indicia. The second portion includes an electrically conductive layer having a touch-sensitive area corresponding to the indicia of the first portion and is arranged to be in register with a corresponding selection area when the closure element is in the closed position.

Abstract: A passivation process includes the successive steps of a) providing a stack having, in succession, a substrate based on crystalline silicon, a layer of silicon oxide, and at least one layer of transparent conductive oxide; and b) applying a hydrogen-containing plasma to the stack, step b) being executed at a suitable temperature so that hydrogen atoms of the hydrogen-containing plasma diffuse to the interface between the substrate and the layer of silicon oxide.

Abstract: Various processes can apply pressure and/or heat to a photovoltaic (PV) layer, including processes that integrate solar cells into different types of industrial glass such as an autoclave lamination process. The disclosure describes a planarization technique that can be used on the PV layer to eliminate point loads caused by such processes. In an aspect, a method for producing a component is described that includes disposing or placing a planarization material on a PV layer, modifying a physical form of the planarization material to provide a planar surface made of the planarization material on one side of the PV layer having surface irregularities, and forming a stack of layers (e.g., as part of an autoclave lamination process) for the component by disposing a first layer over the planar surface on the one side of the PV layer and a second layer over the other, opposite side of the PV layer.

Abstract: An organometallic compound and an organic light-emitting device including the same are provided. The organometallic compound is represented by Formula 1: M(LA)n1(LB)n2.

Abstract: A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.

Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.