Patents Examined by Bo Fan
  • Patent number: 10629625
    Abstract: To provide a novel resistor. To provide a display device having a novel structure that can improve its reliability. To provide a display device having a novel structure that can reduce electrostatic discharge damages. The resistor includes a semiconductor layer and an insulating layer formed over the semiconductor layer, and the semiconductor layer is an oxide represented by an In-M-Zn oxide that contains at least indium (In), zinc (Zn), and M (M is a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) and the insulating layer contains at least hydrogen.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10627481
    Abstract: A system and method are provided for processing echo signals reflected from one of more targets in a radar field-of-view. The method includes receiving echo signals reflected from one or more targets in the radar field-of-view in response to a sequence of transmit pulses; generating a received signal vector containing samples from the received echo signals; and applying the received signal vector to a set of filters configured to calculate a Doppler spectrum for a set of Doppler frequencies to which each filter is tuned, wherein an integration processing time for each filter varies relative to the Doppler frequency of each filter.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 21, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATION LLC
    Inventors: Oded Bialer, Igal Bilik
  • Patent number: 10622359
    Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Salman Latif, Chanaka D. Munasinghe
  • Patent number: 10622715
    Abstract: There is provided mechanisms for beam forming using an antenna array comprising dual polarized elements. A method comprises generating one or two beam ports, wherein the one or two beam ports are defined by combining at least two non-overlapping subarrays. Each subarray has two subarray ports, the two subarray ports having identical power patterns and mutually orthogonal polarization. The at least two non-overlapping subarrays are combined via expansion weights. The expansion weights map the one or two beam ports to subarray ports such that the one or two beam ports have the same power pattern as the subarrays. At least some of the expansion weights have identical non-zero magnitude and are related in phase to form a transmission lobe. The method comprises transmitting signals using said one or two beam ports.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: April 14, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Fredrik Athley, Sven Petersson
  • Patent number: 10615353
    Abstract: A method for manufacturing an organic thin film transistor includes steps of: forming a graphene layer on a surface of a metal substrate; covering a surface of the graphene layer with an organic solution and heating the graphene layer to form organic semiconductor nano lines on the surface of the graphene layer; and transferring the organic semiconductor nano lines to a target substrate. The graphene layer is formed on the surface of the metal substrate in mass production. The organic semiconductor nano lines (monocrystalline semiconductor) are grown in mass production by the graphene layer. The semiconductor layer having organic thin film transistors is formed after transferring the organic semiconductor nano lines on the target substrate. A large amount of the organic semiconductor nano lines can be formed simultaneously on the surface of the metal substrate with a large area.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 7, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Bo Liang, Wei Wang
  • Patent number: 10615164
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-Jung Kim, Min Hee Cho, Bong-Soo Kim, Junsoo Kim, Satoru Yamada, Wonsok Lee, Yoosang Hwang
  • Patent number: 10598817
    Abstract: A method, apparatus, and program product utilize a buffer defined relative to a wellbore trajectory to generate a work zone around a wellbore for use in connection with formation modeling. In some embodiments, for example, a closed curve such as a non-rectangular, polygonal work zone may be defined around a wellbore based upon a buffer that extends generally transverse to the trajectory of a length of a wellbore a predetermined distance. In addition, boundaries may be defined in a work zone to effectively split the work zone into multiple closed curves or polygons in response to user editing, e.g., to create one or more subsurface layers in the work zone. In such instances, points defining a subsurface layer may be shared by adjacent layers such that editing of such points will affect each of the layers sharing such points.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: March 24, 2020
    Assignee: Schlumberger Technology Corporation
    Inventors: Joan Abadie, Adrien Chassard, Mohammad Taghi Salehi, David Maggs, Shahzad Asif, Christopher Edward Morriss, Koji Ito
  • Patent number: 10593871
    Abstract: Methods for forming tunnel barrier layers are provided, including a method comprising exposing a surface of a material, the surface free of oxygen, to an initial water pulse for a pulse time and at a pulse temperature, the pulse time and pulse temperature selected to maximize hydroxylation of the surface; and exposing the hydroxylated surface to alternating, separated pulses of precursors under conditions to induce reactions between the hydroxylated surface and the precursors to form a tunnel barrier layer on the surface of the material via atomic layer deposition (ALD), the tunnel barrier layer having an average thickness of no more than 1 nm and being formed without an intervening interfacial layer between the tunnel barrier layer and the surface of the material.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: March 17, 2020
    Assignee: UNIVERSITY OF KANSAS
    Inventors: Judy Z. Wu, Jamie Wilt, Ryan Goul, Jagaran Acharya
  • Patent number: 10585195
    Abstract: Receiver and method for receiving one or more RF signals, the RF signals comprising a component relative to a direct propagation path and, depending on a propagation environment, one or more additional components relative to reflected propagation paths, the receiver comprising a calculation circuit configured to: compute at least a first correlation function (310) between the received signal and at least a replica of a RF signal generated at the receiver, and for at least an output of said first correlation function: perform a cepstrum transform (410), search for one or more reflected propagation paths from the output of the cepstrum transform (411), and when reflected propagation paths are detected, determine the associated propagation characteristics (412), and remove the contribution of the detected reflected propagation paths from one of the received signal or the output of the first correlation function.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 10, 2020
    Assignee: CENTRE NATIONAL D'ETUDES SPATIALES
    Inventors: François-Xavier Marmet, Joël Dantepal
  • Patent number: 10580947
    Abstract: A package has a first electrode, a second electrode, and a first resin body. The first resin body has a retainer portion and a wall portion. The retainer portion retains the first electrode and the second electrode and forms a bottom portion of the package together with the first electrode and the second electrode. The wall portion surrounds a mounting region on the bottom portion and has a pair of opposite outer sides. Each of the first electrode and the second electrode has an outer lead portion extending outwardly from respective one of the pair of opposite outer sides of the wall portion. The first resin body further has a flange portion having parts extending from the pair of opposite outer sides of the wall portion. Each of the outer lead portions extends outwardly beyond a distal end of the corresponding part of the flange portion in plan view.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 3, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Mayumi Fukuda
  • Patent number: 10581026
    Abstract: The present invention provides a manufacture method of a flexible display panel, and after forming grooves on the rigid substrate, and forming the flexible supporting bases in the grooves, and manufacturing the display element layer on the flexible supporting bases and the rigid substrate, the flexible display mother board is obtained. Then, the normal knife flywheel is used to cut the flexible display mother board along the edges of the grooves to obtain the flexible substrate units. After stripping the rigid substrates in the flexible substrate units with laser, the flexible display substrates are obtained. The method saves the purchase cost of the laser cutting apparatus, and thus to reduce the manufacture cost of the flexible display substrate, and meanwhile, to raise the cutting yield of cutting the flexible display mother board with the normal knife flywheel for promoting the usage lifetime of the knife flywheel.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 3, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Fang Qin
  • Patent number: 10573745
    Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10572629
    Abstract: Methods, computer program products, and systems are described that include accepting at least one attribute of at least one individual, querying at least one database at least partly based on the at least one attribute, selecting from the at least one database at least one prescription medication and at least one artificial sensory experience to address the at least one attribute of at least one individual, and/or presenting an indication of the at least one prescription medication and the at least one artificial sensory experience at least partly based on the selecting from the at least one database at least one prescription medication and at least one artificial sensory experience to address the at least one attribute of at least one individual.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: February 25, 2020
    Assignee: The Invention Science Fund I, LLC
    Inventors: Roderick A. Hyde, Muriel Y. Ishikawa, Eric C. Leuthardt, Royce A. Levien, Robert W. Lord, Mark A. Malamud, Elizabeth A. Sweeney, Lowell L. Wood, Victoria Y. H. Wood
  • Patent number: 10573751
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 10566476
    Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive substrate; a light sensing region on the semiconductive substrate; a waveguide region configured to guide light from a wave insert portion through a waveguide portion and to a sample holding portion; and an interconnect region below the waveguide region, and the interconnect region being disposed above the light sensing region. The waveguide portion includes a first dielectric layer comprising a first refractive index and at least one second dielectric layer comprising a second refractive index, wherein the second refractive index is smaller than the first refractive index.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 18, 2020
    Assignee: PERSONAL GENOMICS, INC.
    Inventors: Teng-Chien Yu, Sheng-Fu Lin, Ming-Sheng Yang
  • Patent number: 10564277
    Abstract: A method for interpolated virtual aperture array radar tracking includes: transmitting first and second probe signals; receiving a first reflected probe signal at a radar array; receiving a second reflected probe signal at the radar array; calculating a target range from at least one of the first and second reflected probe signals; corresponding signal instances of the first reflected probe signal to physical receiver elements of the radar array; corresponding signal instances of the second reflected probe signal to virtual elements of the radar array; interpolating signal instances; calculating a first target angle; and calculating a position of the tracking target relative to the radar array from the target range and first target angle.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: February 18, 2020
    Assignee: Oculii Corp.
    Inventors: Lang Hong, Steven Hong
  • Patent number: 10559678
    Abstract: In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain of the low-side transistor; and the gate of the high-side transistor can be coupled to each of the source and the gate of the low-side transistor. In another aspect, an electronic device can include a high-side transistor, a low-side transistor, and a field electrode. The low-side transistor can include a drain region coupled to the source electrode of the high-side transistor. The field electrode can overlie and be capacitively coupled to a channel layer of the high-side transistor, wherein the field electrode is configured to be at a voltage between the voltages of the high-side and low-side power supply terminals.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: February 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, ALi Salih
  • Patent number: 10551507
    Abstract: A global navigation satellite system (GNSS) receiver including a sequential chip mixed frequency correlator array system (SCMFCAS) is provided. The SCMFCAS includes P signal generators, each receiving N samples of intermediate frequency (IF) data of a GNSS signal. Each signal generator includes a primary mixer, a pseudo random noise code generator, and Q mixed frequency correlators (MFCs). Each MFC generates accumulated correlation components of the N samples of the IF data by processing the N samples of the IF data. Adders and subtractors operably connected to the SCMFCAS are time division multiplexed for generating correlation values of a positive frequency and a negative frequency of the N samples of the IF data by combining the accumulated correlation components. Time division multiplexing the adders and the subtractors across the SCMFCAS and generation of the correlation values reduce logic area of the SCMFCAS, thereby reducing power consumption of the GNSS receiver.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: February 4, 2020
    Assignee: Accord Ideation Private Limited
    Inventors: Gowdayyanadoddi Shivaiah Naveen, Smitha Shrinivasa Nayak, Varsha Bhupal Bavache
  • Patent number: 10539674
    Abstract: A method and apparatus are provided to determine a range of a sling load from a vehicle. In one embodiment, an FMCW RADAR altimeter generates an altitude history image that is used to determine the range of the sling load from the vehicle and an altitude of the vehicle.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 21, 2020
    Assignee: Honeywell International Inc.
    Inventors: Seth T. Frick, David C. Vacanti, Todd R. Burlet
  • Patent number: 10541333
    Abstract: A method for depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include: providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include: exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA dopant precursor; wherein the at least one Group IIIA dopant precursor comprises a borohydride, an organic borohydride, a halide, or an organohalide. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 21, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: John Tolle, Joe Margetis