Abstract: A method of fabricating a semiconductor device includes the steps of modifying a damaged layer containing carbon and formed at a semiconductor surface by exposing the damaged layer to oxygen radicals to form a modified layer, and removing the modified layer by a wet etching process, wherein the modifying step is conducted by adding an active specie of an element that would obstruct formation of double bond between a Si atom and an oxygen atom by causing a chemical bond with Si atoms on the semiconductor surface.

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract: A method and apparatus for identifying defective partially manufactured semiconductor wafers in a manufacturing line is described, wherein defects caused by silicon erosion created by over-etching the wafer can be detected. The method described herein is based on an in-line test of selected structures, such as FETs, located in the kerfs that surround the integrated circuit chips. Leakage current between the gate and the source-drain region is measured at FETs in each kerf. Based on the measurement, a leakage current map is created and compared to a standard map. In accordance with this comparison and to the distribution of patterns of leakage currents, it is determined whether or not the wafer is defective. This determination is performed in the kerfs after formation of the gate and source-drain regions, and prior to the wafer being completed. By detecting defective wafers at an early stage, considerable manufacturing resources are saved.

Abstract: A capacitance coupled, transmission line-fed, radio frequency MEMS switch and its fabrication process using photoresist and other low temperature processing steps are described. The achieved switch is disposed in a low cost dielectric housing free of undesired electrical effects on the switch and on the transmission line(s) coupling the switch to an electrical circuit. The dielectric housing is provided with an array of sealable apertures useful for wet, but hydrofluoric acid-free, removal of switch fabrication employed materials and also useful during processing for controlling the operating atmosphere surrounding the switch—e.g. at a pressure above the high vacuum level for enhanced switch damping during operation. Alternative arrangements for sealing an array of dielectric housing apertures are included. Processing details including plan and profile drawing views, specific equipment and materials identifications, temperatures and times are also disclosed.

Abstract: A method for encapsulating at least one organic light-emitting (OLED) device is disclosed. The method includes the step of forming a concave region on a plate by applying a negative pressure to a predetermined area of the plate. The plate is attached to a substrate including at least one active region such that the concave region of the plate spans over the active region.

Abstract: The present invention relates to a nanotube device (100, 600), comprising a nanotube with a longitudinal and a lateral extension, a structure for supporting at least a first part of the nanotube, and first means for exerting a force upon the nanotube in a first direction defined by its lateral extension. At least a second part of the nanotube protrudes beyond the support of said structure, so that when said force exceeds a certain level, the second part of the nanotube will flex in the direction of its lateral extension, and thereby close a first electrical circuit. Suitably, the first means for exerting said force upon the nanotube is an electrical means, the force being created by applying a voltage to the means.

Abstract: A method for making an OLED device includes providing a substrate having one or more test regions and one or more device regions, moving the substrate into a least one deposition chamber for deposition of at least one organic layer, and depositing the at least one organic layer through a shadowmask selectively onto the at least one device region and at least one test region on the substrate. The method also includes measuring a property of the at least one organic layer in the at least one test region, and adjusting the deposition process in accordance with the measured property.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.

Abstract: Methods for forming metal lines in semiconductor devices are disclosed. One example method may include forming a lower adhesive layer on a semiconductor substrate; forming a metal layer including aluminum on the lower adhesive layer; forming an anti-reflection layer on the metal layer; forming a photomask on the anti-reflection layer; performing an initial etching, a main etching and an over-etching for the anti-reflection layer, the metal layer and the lower adhesive layer, respectively, in a region which is not protected by the photomask, using C3F8 as a main etching gas; and removing the photomask residual on the anti-reflection layer.

Abstract: A novel solid-state imaging device is provided which has a first color picture cell array containing picture cells having a photo-electric converting element for converting incident light to electric signals arranged two-dimensionally, and a second color picture cell array containing picture cells having a photo-electric converting element for converting incident light to electric signals arranged two-dimensionally, placed in juxtaposition, on a substrate. The solid-state imaging device is characterized in that a common well is provided to be common to the first color picture cell array and the second color picture cell array. A well-wiring and a well-contact may be provided as necessary between the first color picture cell array and the second color picture cell array.

Abstract: Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.

Abstract: An OXO-type inter-poly insulator (where X is a high-K metal oxide and O is an insulative oxide) is defined by forming an amorphous metal oxide layer on a silicon-based insulator (e.g., a silicon oxide layer) and then nitridating at least upper and lower sub-layers of the amorphous metal oxide with a low temperature plasma treatment that maintains temperature below the recrystallization temperature of the amorphous material. Such a plasma treatment has been found to improve breakdown voltage characteristics of the insulator. In one embodiment, the metal oxide includes aluminum oxide and it is fluorinated with low temperature plasma prior to nitridation.

Abstract: A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.

Abstract: A semiconductor topography is provided which includes a magnetic field shield layer formed upon a semiconductor device. In particular, the semiconductor topography may include a ferromagnetic layer adapted to shield underlying layers from external magnetic fields. Such a ferromagnetic layer may include either ferrite and/or non-ferrite materials. In some embodiments, the semiconductor topography may include a magnetic field shield layer with a different pattern configuration than an adjacent passivation layer. Consequently, a method for processing a semiconductor topography which includes patterning a magnetic field shield layer to form openings other than bond pad openings within the semiconductor topography is provided.

Abstract: A magnetic random access memory includes a plurality of multi-layered memory structures that are formed within a single memory unit and connected in one of a series and a parallel configuration. Each of the plurality of multi-layered memory structures has a resistance that varies based on a magnetization direction of a ferromagnetic layer. A transistor is operatively coupled to each of the plurality of multi-layered memory structures to perform one of a memory read and a memory write operation based on a conduction state of the transistor.

Abstract: In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.

Abstract: First and second metal foil layers are laminated on opposite surfaces of a first insulating layer to form a first board. Then, the first and second metal foil layers are formed into predetermined conductor patterns respectively. Then, second and third insulating layers of second and third boards formed separately from the first board are laminated on the first and second metal foil layers through first and second adhesive layers respectively. Then, a thin layer portion is removed and thick layer portions are formed into predetermined conductor patterns respectively in third and fourth metal foil layers of the second and third boards.

Abstract: A GaN based LED comprises: a three layer buffer which is a template for growth of a high quality I GaN platform for quality growth of subsequent layers; a light emitting structure; and complementary N and P electrode structures which spread current flowing between the electrodes fully across the light emitting structure.

Abstract: A quantum well structure is provided that includes two or more quantum well layers coupled by at least one barrier layer such that at least one of a piezo-electric field and a pyro-electric field is produced. The quantum well structure is sufficiently doped to cause a Fermi energy to be located between ground states and excited states of the coupled quantum well layers. The quantum well structure can be incorporated into a layered semiconductor to form optical devices such as a laser or optical amplifier.