Abstract: A hybrid structure or device is provided wherein carried on a single substrate is at least one micro-spring interconnect having an elastic material that is initially fixed to a surface of the substrate, an anchor portion which is fixed to the substrate surface and a free portion. The spring contact is self-assembling in that as the free portion is released it moves out of the plane of the substrate. Also integrated on the substrate is a sensor having an active layer and contacts. The substrate and sensor may be formed of materials which are somewhat partially transparent to light at certain infrared wavelengths. The integrated sensor/spring contact configuration may be used in an imaging system to sense output from a light source which is used for image formation. The light source may be a laser array, LED array or other appropriate light source. The sensor is appropriately sized to sense all or some part of light from the light source.

Abstract: An n-type AlAs/n-type Al0.5Ga0.5As DBR layer and a p-type (Al0.2Ga0.8)0.5In0.5P/p-type Al0.5In0.5P DBR layer are formed on an n-type GaAs substrate at specified intervals so that a reflection spectrum is centered at 650 nm and the resonance wavelength becomes 650 nm. A quantum well active layer (light-emitting layer) is formed so that the light emission peak wavelength becomes 650 nm in the belly position of the standing wave generated in a resonator constructed of both the DBR layers. A grating pattern is formed on the surface of a p-type Al0.5Ga0.5As light diffusion layer that serves as a light-emitting surface surrounded by a p-type electrode. By thus roughening the light-emitting surface, light emitted from the light-emitting layer is diffused in various directions, reducing the radiation angle dependency of the emission light wavelength.

Abstract: The present invention discloses a semiconductor light emitting device comprising at least one semiconductor light emitting element of edge-emission type, a first heat sink and a second heat sink, wherein at least a part of an electrode for the first-conduction-type semiconductor of the semiconductor light emitting element is in contact with the first heat sink; at least a part of an electrode for the second-conduction-type semiconductor of the semiconductor light emitting element is in contact with the second heat sink; and the first heat sink and the second heat sink are in contact with each other in a junction overlooking one of the two side planes which do not compose the facets of the cavity in the semiconductor light emitting element.

Abstract: In a semiconductor device and method of manufacturing thereof, a semiconductor device having an SOI structure is provided with a capacitor including a first electrode in an SOI layer, a second electrode opposing the first electrode, and a dielectric film therebetween. An isolation region is provided as contained in the SOI layer to electrically isolate the first electrode from remaining areas of the SOI layer, such as active areas or the like. The method includes forming the isolation regions in the SOI layer, forming the first electrode in the SOI layer as electrically isolated from the remaining areas of the SOI layer by the isolation regions, forming the dielectric film on the first electrode, and forming the second electrode on the dielectric film opposite the first electrode.

Abstract: A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer.

Abstract: To provide a semiconductor wafer having dot marks produced by irradiating laser beam capable of selecting a marking region capable of reading and writing marks in a state in which the marks hardly vanish and the semiconductor wafer is contained in a wafer cassette, inscribing information of an identification number or electric properties in the region and grasping past history by a unit of the wafer in processing steps or semiconductor fabrication steps thereafter, a very small dot mark is formed by irradiating laser having a diameter of 1 through 13 &mgr;m on an inner wall face of a notch (1) formed on an outer peripheral face of a semiconductor wafer (W), particularly on an inclined face of its peripheral edge.

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

Abstract: A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the base and emitter can be quickly removed. This solves the problem in the prior art that using a bias between the base and the emitter to remove holes usually results in a large dark current (bias current), power consumption, and diminishing optoelectronic conversion gain.

Abstract: A surface mount package is composed of a package body and first and second terminals. The package body has first and second surfaces intersecting with each other. Also, the package body has an installing portion for an element to be installed. The first terminal is connected to the first surface, and the second terminal is connected to the second surface.

Abstract: An integrated circuit structure is disclosed wherein the capacitance between nearby conductive portions may be lowered using carbon-containing low k silicon oxide dielectric material, without contributing to the problem of via poisoning, by careful control of the carbon content of the dielectric material in two regions of the integrated circuit structure. The first region comprises the region between adjacent raised conductive lines formed over an underlying insulation layer, where undesirable capacitance may be formed horizontally between such adjacent conductive lines, while the second region comprises the region above the raised conductive lines where vias are normally formed extending upward from the raised conductive lines through the dielectric layer to an overlying layer of metal interconnects.

Abstract: A two-lead, surface-mounting, high-power micro-leadframe semiconductor package has the same outline, mounting, and electrical functionality as industry standard leadframe packages but provides a lower internal resistance, a higher package power rating, and costs less to produce. The novel package incorporates one of a rectangular array of “micro-leadframes” (“MLFs”), each having parallel and respectively coplanar upper and lower surfaces etched in a plate having a uniform thickness. Each micro-leadframe includes an I-shaped die pad having a head, a foot, and opposite sides. First and second leads are disposed at the foot of the die pad, each having a side aligned with one of the sides of the pad. The second lead has an right-angled wire-bonding pad next to the die pad. A portion of a lower surface of each of the die pad and the leads is exposed through a lower surface of an envelope of plastic molded on the package to define package input/output terminals.

Abstract: A plularity of sensor chips, each having strain gauges and a thin diaphragm, are formed on a semiconductor wafer having an upper layer and a lower layer forming a P-N junction plane therebetween. The sensor chips are separated into individual pieces by dicing along column and row interstices dividing the sensor chips. Conductor lines for supplying an electrical voltage for electrochemically etching the diaphragms are formed on and along the interstices. All of the conductor lines are removed by a dicing blade having a wider width than the conductor lines to avoid electrical leakage due to particles of conductor lines leftover on side surfaces of the diced out sensor chips.

Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: The invention relates to a semiconductor device having improved wiring layers. The wiring is formed on the semiconductor substrate and has a first region and a second region. The first region comprises a conductive film and an insulating film formed by oxidizing a film connected to the conductive film and made of the same material thereof. The second region includes a wiring and is provided on the first region. The Gibbs free energy of the wiring decreases less than that of the conductive film when the wiring and the conductive film are oxidized.

Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.

Abstract: A high electron mobility transistor photodetector includes an undoped GaAs buffer, a p-type GaAs layer positioned above the undoped GaAs buffer that is between 0.5 to 1 &mgr;m in thickness, an undoped low temperature GaAs layer positioned above the p-type GaAs layer, an undoped GaAs layer positioned above the low temperature GaAs layer, a layer of undoped InGaAs positioned above the undoped GaAs layer, a layer of undoped AlGaAs positioned above the layer of InGaAs, an n+ AlGaAs charge-suppling layer positioned above the layer of undoped AlGaAs, an n+ GaAs contact layer positioned above the n+ AlGaAs charge-supplying layer, and source and drain ohmic contacts positioned above the n+ GaAs contact layer. A negative bias voltage is applied to the p-type GaAs layer to sweep the holes from the photo-absorptive layer which greatly increases the speed and responsiveness of the device.

Abstract: An active matrix liquid crystal display having improved reliability. Pixel regions and a peripheral driver circuit are integrally packed on the display. TFTs forming the peripheral driver circuit are located inside a sealing material layer on the side of a liquid crystal material, thus protecting the peripheral driver circuit from external moisture and contaminants. This enhances the long-term reliability of the peripheral driver circuit. Pixel TFTs are arranged in pixel regions. The leads going from the TFTs forming the peripheral driver circuit to the pixel TFTs are shortened. This results in a reduction in the resistance. As a result, the display characteristics are improved.

Abstract: A device in which one or more thin film transistors are monolithically integrated with a light emitting diode is disclosed. The thin film transistor has an organic semiconductor layer. The light emitting layer of the light emitting diode is also an organic material. The device is fabricated economically by integrating the fabrication of the thin film transistor and the light emitting diode on the substrate and by employing low cost fabrication techniques.