Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.

Abstract: A compound semiconductor multilayer structure comprising a carbon-containing p-type gallium arsenide (GaAs)-system crystal layer, wherein the carbon-containing p-type GaAs-system crystal layer exhibits a predominant photoluminescence peak measured at 20K within a range of 828 nm to 845 nm, and wherein the ratio of hydrogen atom concentration to carbon atom concentration in the carbon-containing p-type GaAs crystal layer is 1/5 or less. Furthermore, in a photoluminescence measurement at 10K, the carbon-containing GaAs-system p-type crystal layer exhibits a first predominant photoluminescence peak and a second predominant photoluminescence peak due to band gap transitions of GaAs and wherein the second predominant luminescence wavelength has a longer wavelength than the first predominant photoluminescence wavelength and the intensity ratio of the second luminescence peak to the first luminescence peak is within a range from 0.5 to 3.

Abstract: A system of testing wafer process-splits in a semiconductor wafer is provided. A first test is performed on a semiconductor wafer in a plurality of locations to obtain first data. The first data is clustered into a plurality of bins to obtain process-split locations. Second tests are performed on the semiconductor wafer in the process-split locations to obtain second data. The first data and second data arc correlated to determine process-split data.

Abstract: A base of LED includes a negative pole seat and a positive pole seat. The negative pole seat is made of conductive material with a flat negative pole plate at a lower outer side thereof, an integral negative pole body at an inner side thereof, multiple upright negative pole seat grooves at two lateral sides thereof and a negative pole recess at the top thereof respectively. The positive pole seat also is made of conductive material with a flat positive pole plate at the lower outer side thereof, an integral positive pole body at the inner side thereof, multiple seat grooves extending upright from the bottom at two lateral sides thereof. A crystal grain is located at the negative pole recess and a connecting wire at both ends thereof joined to the positive pole seat and the crystal grain and the negative pole plate and the positive pole plate are adhered to circuit of a circuit board to form a close circuit.

Abstract: A buffer layer of aluminum nitride (AlN) about 25 nm thick is provided on a sapphire substrate. An n+ layer of a high carrier density, which is about 4.0 ?m thick and which is made of GaN doped with silicon (Si), is formed on the buffer layer. An intermediate layer of non-doped InxGa1?xN (0<x<1) about 3000 ? thick is formed on the high carrier density n+ layer. Then, an n-type clad layer of GaN about 250 ? thick is laminated on the intermediate layer. Further, three well layers of Ga0.8In0.2N about 30 ? thick each and two barrier layers of GaN about 70 ? thick each are laminated alternately on the n-type clad layer to thereby form a light-emitting layer of a structure with two multilayer quantum well (MQW) cycles.

Abstract: In order to provide a semiconductor device which makes it possible to mount a semiconductor element on the substrate of the semiconductor device main body at the correct position with a higher degree of accuracy, a semiconductor element 2 is mounted at a circuit forming surface of a semiconductor substrate 1 at the periphery of which pad electrodes 5 are provided and a specific area in the semiconductor device containing the semiconductor element 2 is sealed with resin. At the circuit forming surface of the semiconductor substrate 1, reference lines 3 are formed in correspondence to the positions of at least three corners of the semiconductor element 2 to be mounted.

Abstract: Provided is a III-V compound semiconductor having a layer formed from a first III-V compound semiconductor expressed by the general formula InuGavAlwN (where 0?u?1, 0?v?1, 0?w?1, u+v+w=1), a pattern formed on the layer from a material different not only from the first III-V compound semiconductor but also from a second III-V compound semiconductor hereinafter described, and a layer formed on the first III-V compound semiconductor and the pattern from the second III-V compound semiconductor expressed by the general formula InxGayAlzN (where 0?x?1, 0?y?1, 0?x?1, x+y+z=1), wherein the full width at half maximum of the (0004) reflection X-ray rocking curve of the second III-V compound semiconductor is 700 seconds or less regardless of the direction of X-ray incidence. In the III-V compound semiconductor, which is a high quality semiconductor, the occurrence of low angle grain boundaries is suppressed.

Abstract: The present invention provides a nitride semiconductor light emitting device with an active layer of the multiple quantum well structure, in which the device has an improved luminous intensity and a good electrostatic withstanding voltage, thereby allowing the expanded application to various products. The active layer 7 is formed of a multiple quantum well structure containing InaGa1?aN (0?a<1). The p-cladding layer 8 is formed on said active layer containing the p-type impurity. The p-cladding layer 8 is made of a multi-film layer including a first nitride semiconductor film containing Al and a second nitride semiconductor film having a composition different from that of said first nitride semiconductor film. Alternatively, the p-cladding layer 8 is made of single-layered layer made of AlbGa1?bN (0?b?1). A low-doped layer 9 is grown on the p-cladding layer 8 having a p-type impurity concentration lower than that of the p-cladding layer 8.

Abstract: A semiconductor light receiving element has a semiconductor portion. The semiconductor portion includes a substrate, a light detecting portion, and a filter portion. The substrate, the light detecting portion, and the filter portion are provided sequentially in a direction of a predetermined axis. The light detecting portion has a light absorbing layer including a III-V semiconductor layer, a window layer including a III-V semiconductor layer, and an anode semiconductor region. The light absorbing layer is an n or i conductivity type semiconductor layer. The light absorbing layer is provided between a III-V semiconductor layer and the window layer. The light detecting portion is provided on one face of the semiconductor substrate with the III-V semiconductor layer interposed therebetween. The filter portion includes InGaAsP semiconductor layers and III-V semiconductor layers.

Abstract: In accordance with the invention, a light emitting device includes a substrate, a layer of first conductivity type overlying the substrate, a light emitting layer overlying the layer of first conductivity type, and a layer of second conductivity type overlying the light emitting layer. A plurality of vias are formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, or selective growth of the layer of second conductivity type. A set of first contacts electrically contacts the layer of first conductivity type through the vias. A second contact electrically contacts the layer of second conductivity type. In some embodiments, the area of the second contact is at least 75% of the area of the device. In some embodiments, the vias are between 2 and 100 microns wide and spaced between 5 and 1000 microns apart.

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.

Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

Abstract: An organic light emitting device display may be formed that is suitably passivated while still permitting electrical access to cathodes and anodes via electrical contacts. In one embodiment, a barrier layer may be formed over the light emitting material to prevent moisture or other ambient attack. The barrier layer may be covered with other layers to form an outer and inner via down to the cathode or anode to be contacted. A contact metal may be provided to the anode or cathode. The layers over the barrier layer permit patterning and contact formation while the barrier layer adequately protects the light emitting material during those steps and thereafter.

Abstract: A Josephson junction includes first and second electrodes, each of which is formed of superconductive material. The first electrode has a first electrode face. A barrier of the junction extends from the first electrode to the second electrode. The barrier has a first barrier face opposing and adjoining the first electrode face. The barrier is formed of non-superconductive barrier material and superconductive barrier material. A concentration of the superconductive barrier material is greater than zero at the first barrier face, whereby the first barrier face is formed at least partially of the superconductive barrier material.

Abstract: A light-receiving device of a pin junction structure, constituted by a quantum-wave interference layers Q1 to Q4 with plural periods of a pair of a first layer W and a second layer B and carrier accumulation layers C1 to C3. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an even number one fourth of wavelength of quantum-wave of carriers in each of the first layer W and the second layer B existing at the level near the lowest energy level of the second layer B. A &dgr; layer, for sharply varying energy band, is formed at an every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. As a result, when electrons are excited in the carrier accumulation layers C1 to C3, electrons are propagated through the quantum-wave interference layer from the n-layer to the p-layer as a wave, and electric current flows rapidly.

Abstract: A light emitting semiconductor device, which includes a Ga0.9In0.1As0.97 active layer disposed between lower n-Ga0.5In0.5P and upper p-Ga0.5In0.5P cladding layers, being provided with lower and upper GaAs spacing layers each intermediate the active layer and the cladding layer. The active layer is approximately lattice-matched to a GaAs substrate and has a thickness of about 0.1 &mgr;m with a photoluminescence peak wavelength of approximately 1.3 &mgr;m, and the GaAs spacing layers each have a thickness of about 2 nm.

Abstract: A field emission display device and a method of fabricating the same are provided. The field emission display device includes a substrate, a transparent cathode layer, an insulation layer, a gate electrode, a resistance layer, and carbon nanotubes. The transparent cathode layer is deposited on the substrate. The insulation layer is formed on the cathode layer and has a well exposing the cathode layer. The gate electrode is formed on the insulation layer and has an opening corresponding to the well. The resistance layer is formed to surround the surface of the gate electrode and the inner walls of the opening and the well so as to block ultraviolet rays. The carbon nanotube field emitting source is positioned on the exposed cathode layer. An alignment error between the gate electrode and the cathode is removed, and carbon nanotube paste is prevented from remaining during development, thereby preventing current leakage and short circuit between the electrodes and diode emission.

Abstract: An optoelectronic semiconductor package device includes a semiconductor chip, an insulative housing and a conductive trace, wherein the chip includes an upper surface and a lower surface, the upper surface includes a light sensitive cell and a conductive pad, the insulative housing includes a first single-piece non-transparent insulative housing portion that contacts the lower surface and is spaced from the light sensitive cell and a second transparent insulative housing portion that contacts the first housing portion and the light sensitive cell, and the conductive trace extends outside the insulative housing and is electrically connected to the pad inside the insulative housing.

Abstract: A lead frame is described which has at least one integrated electronic circuit. The integrated electronic circuit is situated in a region of a main area of the lead frame. The lead frame has at least one signal line, at least one electrically insulating plate, and an electrically conductive, grounded plate are situated. The electrically insulating plate, and the electrically conductive, grounded plate are situated, at least in sections, between the integrated electronic circuit and the signal line. A method for producing the lead frame is also described.

Abstract: A compound semiconductor device includes an emitter layer, a base layer which is in contact with the emitter layer and formed of a first compound semiconductor, a collector layer which is in contact with the base layer and formed of a second compound semiconductor having a wider bandgap than that of the first compound semiconductor. In the device, a delta doped layer having a higher concentration of an impurity than that of the collector layer is formed at the heterojunction interface between the collector layer and the base layer or in a region of the collector layer located at about 10 nm or less from the heterojunction interface with the base layer.