Patents Examined by Brandon C Fox
  • Patent number: 11950489
    Abstract: A deposition mask for manufacturing a display panel includes a metallic base having a thickness of about 50 micrometers to about 200 micrometers and a plurality of openings defined therein, wherein at least some of the openings include a first opening having a first width and a second opening having a second width smaller than the first width respectively defined along a thickness direction of the metallic base, and wherein the metallic base includes a first part in which the first opening is defined, and a second part in which the second opening is defined, the second part having a width that increases in a direction downward from a top surface of the metallic base along the thickness direction of the metallic base.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: April 2, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyu Hwan Hwang, Jeongkuk Kim, Hwi Kim, Kanghyun Nam, Sangha Park, Areum Lee, Da-Hee Jeong, Eunbee Jo, Seungmin Jin, Jaemin Hong
  • Patent number: 11949029
    Abstract: A transparent multi-layer assembly includes a transparent carrier structure comprising a polymer material and an electrically conductive transparent layer comprising an electrically conductive oxide. A silicon carbide layer is arranged as an adhesion promoter between the transparent carrier structure and the electrically conductive transparent layer.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: April 2, 2024
    Assignee: Albert-Ludwigs-Universit├Ąt Freiburg
    Inventors: Max Eickenscheidt, Annette Mittnacht, Thomas Stieglitz, Marie T. Alt
  • Patent number: 11946158
    Abstract: An apparatus for growing semiconductor wafers, in particular of silicon carbide, wherein a chamber houses a collection container and a support or susceptor arranged over the container. The support is formed by a frame surrounding an opening accommodating a plurality of arms and a seat. The frame has a first a second surface, opposite to each other, with the first surface of the frame facing the support. The arms are formed by cantilever bars extending from the frame into the opening, having a maximum height smaller than the frame, and having at the top a resting edge. The resting edges of the arms define a resting surface that is at a lower level than the second surface of the frame. The seat has a bottom formed by the resting surface.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: April 2, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ruggero Anzalone, Nicolo' Frazzetto, Francesco La Via
  • Patent number: 11937477
    Abstract: A display device includes pixel circuits disposed on a substrate, each of the pixel circuits comprising a transistor and a storage capacitor, display elements electrically connected to the pixel circuits, and a metal layer disposed between the substrate and the pixel circuits, the metal layer comprising through-holes, wherein the through-holes of the metal layer include a first through-hole, and a second through-hole disposed adjacent to the first through-hole.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Eunkyung Koh, Seungin Baek, Sanggu Lee, Daewook Kim, Byongug Park, Hyunjin Son, Jewon Yoo, Sujin Choi
  • Patent number: 11937511
    Abstract: Aspects of the subject disclosure include a pressure-sensing device consisting of a housing including a membrane and one or more piezoresistive elements disposed on the membrane to sense a displacement due to a deflection of the membrane. A first set of electrodes is disposed over the membrane, and a second set of electrodes is disposed on a permeable port of the device at a distance from the membrane. The first and second sets of electrodes form an electrostatic actuator to exert a repulsive force onto the membrane to reduce the deflection of the membrane.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: March 19, 2024
    Assignee: Apple Inc.
    Inventors: Majid Khan, Roberto M. Ribeiro, Savas Gider
  • Patent number: 11935829
    Abstract: In some implementations, one or more semiconductor processing tools may form a via for a semiconductor device. The one or more semiconductor processing tools may deposit a metal plug within the via. The one or more semiconductor processing tools may deposit an oxide-based layer on the metal plug within the via. The one or more semiconductor processing tools may deposit a resistor on the oxide-based layer within the via. The one or more semiconductor processing tools may deposit a first landing pad and a second landing pad on the resistor within the via. The one or more semiconductor processing tools may deposit a first metal plug on the first landing pad and a second metal plug on the second landing pad.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chi-Han Yang
  • Patent number: 11930628
    Abstract: A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-I Shih, Ren-Hua Guo
  • Patent number: 11917830
    Abstract: A NAND ferroelectric memory cell with a three-dimensional structure and a preparation method thereof are provided, the ferroelectric memory cell comprises: an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer, and/or a gate buffer layer, and a gate arranged successively from the inside to the outside. In the memory cell of the present disclosure, the buffer layer has the following effects: 1. It can induce the crystallization of ferroelectric film to form ferroelectric phase; 2. It can reduce adverse effects caused by different crystalline characteristics of the channel layer and the ferroelectric layer, improve the quality and uniformity of the deposited film; 3. It can enhance the interface property of the channel layer, reduce leakage current, and enhance endurance of the device. Therefore, the buffer layer can improve the overall storage property and homogeneity of memory cells with a three-dimensional structure.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: February 27, 2024
    Assignee: XIANGTAN UNIVERSITY
    Inventors: Min Liao, Siwei Dai, Yanwei Huan, Qijun Yang, Zhaotong Liu, Yichun Zhou
  • Patent number: 11912563
    Abstract: A micromechanical component, whose diaphragm is supported and has support structures on its inner diaphragm side. Each of the support structures includes a first and second edge element structure, and at least one intermediate element structure positioned between the first and second edge element structures. For each of the support structures, a plane of symmetry is definable, with respect to which at least the first edge element structure of the respective support structure and the second edge element structure of the respective support structure are specularly symmetric. In each of support structures, a first maximum dimension of its first edge element structure perpendicular to its plane of symmetry and a second maximum dimension of its second edge element structure perpendicular to its plane of symmetry are greater than the maximum dimension of its intermediate element structure perpendicular to its plane of symmetry.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: February 27, 2024
    Assignee: ROBERT BOSCH GMBH
    Inventors: Hans Artmann, Christoph Hermes, Heribert Weber, Jochen Reinmuth, Peter Schmollngruber, Thomas Friedrich
  • Patent number: 11901263
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 11903214
    Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: TsuChing Yang, Hung-Chang Sun, Kuo Chang Chiang, Sheng-Chih Lai, Yu-Wei Jiang
  • Patent number: 11903287
    Abstract: A light-emitting element includes: pixel electrodes provided for individual subpixels of at least three colors; a common electrode provided facing each of the pixel electrodes; and light-emitting layers of each color provided between the common electrode and, respectively, each of the pixel electrodes, wherein one of each of the pixel electrodes and the common electrode is a cathode electrode and the other is an anode electrode and among the light-emitting layers of the at least three colors, a light-emitting layer of a color having a largest electron affinity extends in a state of being layered between the cathode electrode and each light-emitting layer of the other colors as well.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasushi Asaoka, Tsuyoshi Kamada, Shigeru Aomori
  • Patent number: 11894394
    Abstract: An array substrate, a method for preparing the array substrate, and a backlight module are disclosed. Before electroplating a first metal layer on a pattern of a seed layer, the method further includes: forming a pattern of a compensation electrode wire electrically connected with a lead electrode on a side, where the lead electrode is formed, of a base substrate. The compensation electrode wire is at least on a second side of a wiring region, the pattern of the lead electrode is formed at a first side of the wiring region, and the first side and the second side are different sides. In the electroplating process, the lead electrode is connected with a negative pole of a power supply, the compensation electrode wire is electrically connected with the lead electrode, thus an area of an electroplating negative pole generating electric field lines is increased by utilizing the compensation electrode wire.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: February 6, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zhanfeng Cao, Yingwei Liu, Ke Wang, Guocai Zhang, Jianguo Wang, Zhiwei Liang, Haixu Li, Muxin Di
  • Patent number: 11881423
    Abstract: Electrostatic chucks (ESCs) for plasma processing chambers, and methods of fabricating ESCs, are described. In an example, a substrate support assembly includes a ceramic bottom plate having heater elements therein. The substrate support assembly also includes a ceramic top plate having an electrode therein. A metal layer is between the ceramic top plate and the ceramic bottom plate. The ceramic top plate is in direct contact with the metal layer, and the metal layer is in direct contact with the ceramic bottom plate.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: January 23, 2024
    Assignee: Applied Materials, Inc.
    Inventor: Vijay D. Parkhe
  • Patent number: 11881462
    Abstract: A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Honglin Guo
  • Patent number: 11871581
    Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Huang-Lin Chao
  • Patent number: 11862933
    Abstract: A method of forming an electrical metal contact within a semiconductor layer stack of a vertical cavity surface emitting laser includes forming a contact hole into the semiconductor layer stack. The contact hole has a bottom and a side wall extending from the bottom. The method further includes providing a photoresist mask inside the contact hole. The photoresist mask covers the side wall of the contact hole and has an opening extending to the bottom of the contact hole. The method additionally includes wet-chemical isotropic etching the bottom of the contact hole, depositing a metal on the bottom of the contact hole, and removing the photoresist mask so that the metal on the bottom of the contact hole is left as the electrical metal contact.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: January 2, 2024
    Assignee: TRUMPF PHOTONIC COMPONENTS GMBH
    Inventors: Roman Koerner, Alexander Weigl
  • Patent number: 11862742
    Abstract: A photodetector for detecting deep ultra-violet light includes a substrate; first and second electrodes separated by a channel; and colloidal MnO based quantum dots formed in the channel. The colloidal MnO based quantum dots are sensitive to ultra-violet light having a wavelength lower than 300 nm.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 2, 2024
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Iman S. Roqan, Somak Mitra, Yusin Pak
  • Patent number: 11851785
    Abstract: An electrical device includes an aluminum nitride passivation layer for a mercury cadmium telluride (Hg1-xCdxTe) (MCT) semiconductor layer of the device. The AlN passivation layer may be an un-textured amorphous-to-polycrystalline film that is deposited onto the surface of the MCT in its as-grown state, or overlying the MCT after the MCT surface has been pre-treated or partially passivated, in this way fully passivating the MCT. The AlN passivation layer may have a coefficient of thermal expansion (CTE) that closely matches the CTE of the MCT layer, thereby reducing strain at an interface to the MCT. The AlN passivation layer may be formed with a neutral inherent (residual) stress, provide mechanical rigidity, and chemical resistance to protect the MCT.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 26, 2023
    Assignee: Raytheon Company
    Inventors: Andrew Clarke, David R. Rhiger, George Grama, Stuart B. Farrell
  • Patent number: 11856786
    Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Yi-Ching Liu, Sai-Hooi Yeong, Yih Wang, Yu-Ming Lin