Abstract: It is an object to provide a technique allowing for suppression of the height of a protrusion from the surface of a semiconductor module. A semiconductor device includes: a semiconductor module having a first groove; a Belleville washer having a recess in an outer surface and a protrusion on an inner surface; and a screw passing through the hole of the Belleville washer and the first groove of the semiconductor module to fasten the semiconductor module and an attached body. A head of the screw is accommodated in the recess of the Belleville washer, and at least portion of the protrusion of the Belleville washer is accommodated in the first groove of the semiconductor module.

Abstract: This invention relates to a method for producing films of semiconducting material based on the organic-inorganic metal-halide compounds with perovskite-like structure, which can be used as a light-absorbing layer in solar cells, including thin-film, flexible and tandem solar cells, as well as can be applied for optoelectronic devices, in particular, light emitting diodes. The method is comprising the following steps: (a) applying a layer of a precursor, (b) applying a layer of composite reagent, and (c) treatment of the applied layers by the reagent X2 wherein the composite reagent applied in the step b) contains a mixture of AX and X2 reagents, and the film obtained after the step b) contains the seeds of the phase with a perovskite-like structure; the reagent AX is a salt comprising cation A+ and anion X?, and the anion X? is a singly charged anion; the reagent X2 is a molecular halogen.

Abstract: The present disclosure provides a precursor solution of an indium gallium zinc oxide film and a method of preparing an indium gallium zinc oxide thin film transistor. The precursor solution is provided with an indium salt, a gallium salt, a zinc salt, a stabilizing agent, and a solvent. The stabilizing agent is ethanolamine. Use of ethanolamine helps to promote an oxidation process of the precursor solution, and reduce an oxygen vacancy concentration in the indium gallium zinc oxide film, so as to improve negative bias of a threshold voltage of a channel layer made of the indium gallium zinc oxide film in a thin film transistor.

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.

Abstract: One example described herein includes an integrated circuit (IC) package. The IC package includes a semiconductor die comprising an IC and an IC package enclosure that substantially encloses the semiconductor die. The IC package also includes at least one conductive metal contact. Each of the at least one conductive metal contact is coupled to the semiconductor die and comprises a planar solder surface exterior to the IC package enclosure to which the respective at least one metal contact is soldered to an external conductive metal contact. The planar solder surface includes at least one solder surface feature.

Abstract: An electronic device is provided. The electronic device includes a sensing element and a display panel. The display panel has a first region and a second region adjacent to the first region. The sensing element is disposed corresponding to the first region and configured to receive a light through the first region. In addition, the display panel includes a plurality of first light absorbing patterns and a plurality of second light absorbing patterns disposed in the second region. The plurality of first light absorbing patterns and the plurality of second light absorbing patterns are configured to absorb different colors of lights. An area of one of the plurality of first light absorbing patterns is different from an area of one of the plurality of second light absorbing patterns.

Abstract: A transparent display device may minimize or reduce coupling occurring between signal lines and apply a repair structure to a scan line. The transparent display device comprises a substrate provided with a transmissive area and a plurality of subpixels disposed between the transmissive areas, first and second anode electrodes provided in each of the plurality of subpixels, a first connection electrode connecting the first anode electrode with the second anode electrode, a driving transistor provided in each of the plurality of subpixels, and a second connection electrode provided below the driving transistor, electrically connecting the driving transistor with the first connection electrode.

Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Abstract: A photoelectric device includes a first photoelectric conversion layer including a heterojunction that includes a first p-type semiconductor and a first n-type semiconductor, a second photoelectric conversion layer on the first photoelectric conversion layer and including a heterojunction that includes a second p-type semiconductor and a second n-type semiconductor. A peak absorption wavelength (?max1) of the first photoelectric conversion layer and a peak absorption wavelength (?max2) of the second photoelectric conversion layer are included in a common wavelength spectrum of light that is one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, a blue wavelength spectrum of light, a near infrared wavelength spectrum of light, or an ultraviolet wavelength spectrum of light, and a light-absorption full width at half maximum (FWHM) of the second photoelectric conversion layer is narrower than an FWHM of the first photoelectric conversion layer.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of carbon-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The substrate may include an exposed region of a first dielectric material and an exposed region of a metal-containing material. The layer of carbon-containing material may be selectively formed over the exposed region of the metal-containing material. Forming the layer of carbon-containing material may include one or more cycles of providing a first molecular species that selectively couples with the metal-containing material. Forming the layer of carbon-containing material may include providing a second molecular species that selectively couples with the first molecular species. The methods may include selectively depositing a second dielectric material on the exposed region of the first dielectric material.

Abstract: A magnetic recording layer according to this embodiment has a magnetic domain wall inside and contains a rare gas element.

Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.

Abstract: A display device is disclosed. In one aspect, the display device includes a flexible substrate capable of being bent in a first direction and an insulating layer including a first opening pattern positioned on the flexible substrate and extending in a second direction crossing the first direction.

Abstract: An image sensor includes: a pixel substrate that includes a plurality of pixels each having a photoelectric conversion unit that generates an electric charge through photoelectric conversion executed on light having entered therein and an output unit that generates a signal based upon the electric charge and outputs the signal; and an arithmetic operation substrate that is laminated on the pixel substrate and includes an operation unit that generates a corrected signal by using a reset signal generated after the electric charge in the output unit is reset and a photoelectric conversion signal generated based upon an electric charge generated in the photoelectric conversion unit and executes an arithmetic operation by using corrected signals each generated in correspondence to one of the pixels.

Abstract: A solid-state image sensor includes a first color filter and a second color filter having different thicknesses and configured to transmit light in predetermined wavelength regions, light-receiving devices configured to receive the light in the predetermined wavelength regions passing through the first color filter and the second color filter, and a light amount compensator configured to compensate for an amount of the light passing through the first color filter or the second color filter.

Abstract: Provided is a stable CdZnTe monocrystalline substrate having a small leakage current even when a high voltage is applied and having a lower variation in resistivity with respect to variations in applied voltage values. A semiconductor wafer comprising a cadmium zinc telluride monocrystal having a zinc concentration of 4.0 at % or more and 6.5 at % or less and a chlorine concentration of 0.1 ppm by mass or more and 5.0 ppm by mass or less, wherein the semiconductor wafer has a resistivity of 1.0×107 ?cm or more and 1.0×108 ?cm or less when a voltage of 900 V is applied, and wherein a ratio (variation ratio) of the resistivity at application of 0 V to the resistivity at application of a voltage of 900 V is 20% or less.

Abstract: A transparent multi-layer assembly includes a transparent carrier structure comprising a polymer material and an electrically conductive transparent layer comprising an electrically conductive oxide. A silicon carbide layer is arranged as an adhesion promoter between the transparent carrier structure and the electrically conductive transparent layer.

Abstract: An apparatus for growing semiconductor wafers, in particular of silicon carbide, wherein a chamber houses a collection container and a support or susceptor arranged over the container. The support is formed by a frame surrounding an opening accommodating a plurality of arms and a seat. The frame has a first a second surface, opposite to each other, with the first surface of the frame facing the support. The arms are formed by cantilever bars extending from the frame into the opening, having a maximum height smaller than the frame, and having at the top a resting edge. The resting edges of the arms define a resting surface that is at a lower level than the second surface of the frame. The seat has a bottom formed by the resting surface.

Abstract: A deposition mask for manufacturing a display panel includes a metallic base having a thickness of about 50 micrometers to about 200 micrometers and a plurality of openings defined therein, wherein at least some of the openings include a first opening having a first width and a second opening having a second width smaller than the first width respectively defined along a thickness direction of the metallic base, and wherein the metallic base includes a first part in which the first opening is defined, and a second part in which the second opening is defined, the second part having a width that increases in a direction downward from a top surface of the metallic base along the thickness direction of the metallic base.