Abstract: The present invention relates to a method for manufacturing a solar cell, comprising: a seating process of seating, in a processing space for manufacturing a solar cell, a cell in which a plurality of thin film layers are formed; a coating process of spraying a conductive material onto the cell; and a scribing process of irradiating a laser toward the cell to form a cell separation unit for separating the cell into a plurality of unit cells.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Abstract: The various embodiments described herein include methods, devices, and systems for fabricating and operating diodes. In one aspect, an electrical circuit includes: (1) a diode component having a particular energy band gap; (2) an electrical source electrically coupled to the diode component and configured to bias the diode component in a particular state; and (3) a heating component thermally coupled to a junction of the diode component and configured to selectively supply heat corresponding to the particular energy band gap.

Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first di electric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.

Abstract: A display panel and a mobile terminal are provided. Number of second sub-pixels in a second pixel repeating unit in a second display area of the display panel is same as number of first sub-pixels in a first pixel repeating unit. The second sub-pixels in the second pixel repeating unit are arranged in a way of gathering together with respect to the first sub-pixels in the first pixel repeating unit. A cathode inhibition block is disposed on an opening in a cathode layer and is located between any adjacent ones of the second pixel repeating units.

Abstract: The present invention provides a resin molded product production method that can reduce the molding defects even when resin-molding is performed in a state where a chip is temporarily bonded to a carrier via a temporary bonding sheet. The method for producing a resin molded product obtained by subjecting an object to be molded being a chip 21 temporarily bonded to a carrier 11 via a temporary bonding sheet 12 to transfer molding, including the step of: resin-molding the object to be molded by transfer molding using a molding die 1000, wherein the resin-molding is performed in a state where a gap G is formed so that the temporary bonding sheet 12 disposed in the molding die 1000 and a surface facing the temporary bonding sheet 12 on a side where the chip 21 is temporarily bonded do not come into contact with each other.

Abstract: A light-emitting diode chip is provided and includes: a first doping-type semiconductor layer, a second doping-type semiconductor layer, and a multiple quantum well structure layer formed between the first doping-type semiconductor layer and the second doping-type semiconductor layer. The multiple quantum well structure layer includes multiple first quantum well structures and at least one second quantum well structure stacked in a distance direction of the first and second doping-type semiconductor layers. The first quantum well structures are used to emit first color light, and the at least second well structure is used to emit second color light different from the first color light. A total number of well layer of the at least one second quantum well structure is 1/15˜? of a total number of well layer of the first quantum well structures located between the at least one second quantum well structure and the second doping-type semiconductor layer.

Abstract: A sensor, such as a piezoelectric MEMS vibration sensor, includes a frame, a beam array comprising a plurality of beams, and a plurality of masses. Each beam of the plurality of beams has an anchored end and an unanchored end, with each beam being coupled to the frame at the anchored end. The unanchored end of each beam is coupled to a respective mass of the plurality of masses. Each beam of the plurality of beams can be configured to minimize a variation in a voltage output for a limited frequency range. In some implementations, the resonant frequency of each beam corresponds to a sensitivity peak in a limited frequency range.

Abstract: A magnetoresistance memory device includes a first conductor, a first insulator covering a side surface of the first conductor, a second conductor on the first conductor that are substantially made of a non-magnetic non-nitrogen material. The device includes a variable resistance material, a third conductor, a first ferromagnetic layer, an insulating layer, and a second ferromagnetic layer. The third conductor, a fourth conductor on the second ferromagnetic layer, and a second insulator covering side surfaces of the first and second ferromagnetic layers and insulating layer are substantially made of a non-nitrogen material. A third insulator is on the second insulator.

Abstract: To provide a solid-state imaging element capable of further improving reliability. Provided is a solid-state imaging element including at least a first photoelectric conversion section, and a semiconductor substrate in which a second photoelectric conversion section is formed, in this order from a light incidence side, in which the first photoelectric conversion section includes at least a first electrode, a photoelectric conversion layer, a first oxide semiconductor layer, a second oxide semiconductor layer, and a second electrode in this order, and a film density of the first oxide semiconductor layer is higher than a film density of the second oxide semiconductor layer.

Abstract: A semiconductor device according to the present embodiment includes a substrate and a semiconductor chip. The substrate has a first face and a plurality of conductive connection parts provided on the first face. The semiconductor chip has a second face that faces the first face and a plurality of connection bumps provided on the second face and electrically connected to the plurality of conductive connection parts. The conductive connection part arranged in a chip outer peripheral region of a chip region on the first face where the semiconductor chip is arranged is different in thickness from the conductive connection part arranged in a chip central region of the chip region.

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

Abstract: Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.

Abstract: The present application provides a pixel structure and a display panel. Each of a plurality of sub-pixel units includes a main sub-pixel, at least one secondary sub-pixel, and a thin film transistor electrically connecting the main sub-pixel and the at least one secondary sub-pixel, wherein by controlling a pretilt angle of a first branch electrode of the main sub-pixel to be different from a pretilt angle of a second branch electrode of the secondary sub-pixel, a driving voltage of the main sub-pixel and a driving voltage of the secondary sub-pixel are different, so that color shift can be effectively alleviated and wider viewing angles can be obtained, thus being beneficial to improve an aperture ratio and light transmission of the pixel structure.

Abstract: Some embodiments include an integrated assembly having a CMOS-containing base containing wordline-driver-circuitry. The wordline-driver-circuitry is subdivided amongst horizontally-extending sub-wordline-driver (SWD) units. Memory cells are over the base, and are arranged in vertically-extending rows. Each of the memory cells includes an access device and a storage element coupled with the access device. Wordlines extend vertically along the rows. Each of the SWD units is associated with at least two of the wordlines and is configured to simultaneously activate the associated wordlines.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of work function metal layers and an oxygen absorbing layer over a channel region of the semiconductor device, including forming a first work function metal layer over the channel region, forming an oxygen absorbing layer over the first work function metal layer, forming a second work function metal layer over the oxygen absorbing layer. A gate electrode metal layer is formed over the plurality of work function metal layers. The work function metal layers, oxygen absorbing layer, and gate electrode metal layer are made of different materials.

Abstract: A design process is used for designing a device comprising a plurality of micro-machined elements, each comprising a flexible membrane, the elements being arranged in a plane in a determined topology. The design process comprises a step of defining the determined topology so that it has a character compatible with a generic substrate having cavities, the characteristics of which are pre-established. Each flexible membrane of the micro-machined elements is associated with one cavity of the generic substrate. The present disclosure also relates to a fabrication process for fabricating a device comprising a plurality of micro-machined elements, and to this device itself, wherein only some of the pairs of cavities and flexible membranes are configured to form a set of functional micro-machined elements.

Abstract: A composite interface transport material-based perovskite photovoltaic, light emission and light detection multi-functional device and a preparation method therefor. The multi-functional device comprises a transparent conductive glass, a composite electron transport layer, a perovskite active layer, a composite hole transport layer and a metal electrode layer which are sequentially arranged in a stacked manner from bottom to top. The work functions of the interface transport layers are adjusted by means of the multi-element interface transport materials, so that the work functions of the electron transport layer and the hole transport layer are respectively levelled with conduction band and valence band positions of the perovskite active layer. According to experiment result comparisons, the photoelectric conversion efficiency and the luminous efficiency of the perovskite multi-functional device, after energy band regulation, are significantly increased.

Abstract: Methods of processing thin film by oxidation at high pressure are described. The methods are generally performed at pressures greater than 2 bar. The methods can be performed at lower temperatures and have shorter exposure times than similar methods performed at lower pressures. Some methods relate to oxidizing tungsten films to form self-aligned pillars.

Abstract: A mask assembly includes a mask frame through which a plurality of openings is defined and a plurality of cell masks disposed to respectively correspond to the cell openings. Each of the cell masks includes a mask main body substantially parallel to a plane defined by a first direction and a second direction crossing the first direction, where a plurality of holes is defined through the mask main body, a bonding portion disposed along an edge of the mask main body, and a tensile portion extending from the bonding portion and disposed spaced apart from the mask main body. The tensile portion includes first tensile portions spaced apart from each other in the first direction and disposed at opposite sides of the mask main body and second tensile portions spaced apart from each other in the second direction and disposed at opposite sides of the mask main body.