Patents Examined by Brandon C Fox
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Patent number: 11690273Abstract: A photo transistor and a display device employing the photo transistor are provided. The photo transistor includes a gate electrode disposed on a substrate, a gate insulating layer that electrically insulates the gate electrode, a first active layer overlapping the gate electrode and including metal oxide, wherein the gate insulating layer is disposed between the gate electrode and the active layer, a second active layer disposed on the first active layer and including selenium, and a source electrode and a drain electrode respectively electrically connected to the second active layer.Type: GrantFiled: December 9, 2020Date of Patent: June 27, 2023Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Tae Sang Kim, Hyun Jae Kim, Hyuk Joon Yoo, Jun Hyung Lim
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Patent number: 11682745Abstract: In a described example, an apparatus includes: a photon detector array with a first signal output pad coupled to a photon detector array pixel; a die carrier comprising a readout integrated circuit (ROIC) die and a conductor layer having conductors that couple a first signal input pad on the conductor layer to an input signal lead of the ROIC die; and the first signal output pad coupled to the first signal input pad.Type: GrantFiled: May 27, 2020Date of Patent: June 20, 2023Assignee: Texas Instruments IncorporatedInventors: Eduardo Bartolome, Rakul Viswanath
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Patent number: 11682746Abstract: There are provided methods of growing arrays of light emitters on substrates. An example method includes adjusting a growth parameter of a given light emitter of an array of light emitters on a substrate to obtain an adjusted growth parameter. The adjusting may be based on a location of the given light emitter on the substrate. The adjusting may be to compensate for nonuniformity in a growth profile of the light emitters across the substrate. The nonuniformity may be associated with a corresponding nonuniformity among wavelengths of light generated by the light emitters. Adjusting the growth parameter may be to adjust the corresponding nonuniformity. The method may also include growing the given light emitter on the substrate based on the adjusted growth parameter. Arrays of corresponding light emitters are also described.Type: GrantFiled: September 29, 2020Date of Patent: June 20, 2023Assignee: DIFTEK LASERS, INC.Inventor: Douglas R. Dykaar
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Patent number: 11653534Abstract: A display device includes pixel circuits disposed on a substrate, each of the pixel circuits comprising a transistor and a storage capacitor, display elements electrically connected to the pixel circuits, and a metal layer disposed between the substrate and the pixel circuits, the metal layer comprising through-holes, wherein the through-holes of the metal layer include a first through-hole, and a second through-hole disposed adjacent to the first through-hole.Type: GrantFiled: September 29, 2020Date of Patent: May 16, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Eunkyung Koh, Seungin Baek, Sanggu Lee, Daewook Kim, Byongug Park, Hyunjin Son, Jewon Yoo, Sujin Choi
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Patent number: 11653568Abstract: An integrated circuit is described herein that includes a semiconductor substrate. First and second piezoresistive sensors are on or in the substrate where each have a respective sensing axis extending in first and second directions respectively parallel with a surface of the substrate, where the second direction is perpendicular to the first direction. A third piezoresistive sensor is on or in the substrate and has a respective sensing axis extending in a third direction parallel with the surface of the substrate and neither parallel nor perpendicular to the first and second directions.Type: GrantFiled: December 29, 2020Date of Patent: May 16, 2023Assignee: Texas Instmments IncorporatedInventors: Baher Haroun, Tobias Bernhard Fritz, Michael Szelong, Ernst Muellner
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Patent number: 11653502Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.Type: GrantFiled: December 2, 2019Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Shriram Shivaraman, Seung Hoon Sung, Ashish Verma Penumatcha, Uygar E. Avci
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Patent number: 11631629Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.Type: GrantFiled: April 28, 2022Date of Patent: April 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
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Patent number: 11626278Abstract: Exemplary methods of semiconductor processing may include providing a boron-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the boron-containing precursor and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a boron-and-carbon-containing layer on the substrate.Type: GrantFiled: March 24, 2021Date of Patent: April 11, 2023Assignee: Applied Materials, Inc.Inventors: Bo Qi, Zeqing Shen, Abhijit Basu Mallick
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Patent number: 11626466Abstract: A display device includes a display panel including a substrate including a front display region, a side display region extending from a side of the front display region, and a transmission region including at least a portion overlapping the front display region in a plan view; and a sensor located on a bottom of the substrate, the sensor having at least a portion overlapping the transmission region in a plan view. The display panel includes first pixels in the front display region; a load compensation element in the side display region; and a connection line electrically connecting the first pixels and the load compensation element by detouring the transmission region.Type: GrantFiled: September 23, 2020Date of Patent: April 11, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Seung Lyong Bok, Sun Mi Yu
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Patent number: 11621268Abstract: A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.Type: GrantFiled: August 5, 2021Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-I Shih, Ren-Hua Guo
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Patent number: 11615988Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.Type: GrantFiled: September 23, 2021Date of Patent: March 28, 2023Assignee: Tessera, LLCInventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
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Patent number: 11610896Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.Type: GrantFiled: April 30, 2021Date of Patent: March 21, 2023Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Taejin Park, Yoosang Hwang
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Patent number: 11605774Abstract: Aspects of the subject technology relate to an apparatus including a housing, one or more piezoresistive elements and a magnetic actuator. The housing includes a membrane, and the piezoresistive elements are disposed on the membrane to sense a displacement due to a deflection of the membrane. The magnetic actuator is disposed inside a cavity of the housing. The magnetic actuator exerts a repulsive force onto the membrane to reduce the deflection of the membrane.Type: GrantFiled: September 23, 2020Date of Patent: March 14, 2023Assignee: Apple Inc.Inventors: Majid Khan, Roberto M. Ribeiro, Savas Gider
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Patent number: 11605730Abstract: A self-aligned short-channel SASC electronic device includes a first semiconductor layer formed on a substrate; a first metal layer formed on a first portion of the first semiconductor layer; a first dielectric layer formed on the first metal layer and extended with a dielectric extension on a second portion of the first semiconductor layer that extends from the first portion of the first semiconductor layer, the dielectric extension defining a channel length of a channel in the first semiconductor layer; and a gate electrode formed on the substrate and capacitively coupled with the channel. The dielectric extension is conformally grown on the first semiconductor layer in a self-aligned manner. The channel length is less than about 800 nm, preferably, less than about 200 nm, more preferably, about 135 nm.Type: GrantFiled: January 16, 2019Date of Patent: March 14, 2023Assignee: NORTHWESTERN UNIVERSITYInventors: Mark C. Hersam, Vinod K. Sangwan, Megan E. Beck
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Patent number: 11598022Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping that changes from a first conductivity type to a second conductivity type on a surface of a substrate or a preceding layer in a reaction chamber from the vapor phase from an epitaxial gas flow comprising a carrier gas, at least one first precursor for an element from main group III, and at least one second precursor for an element from main group V, wherein when a first growth height is reached, a first initial doping level of the first conductivity type is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor, then the first initial doping level is reduced to a second initial doping level of the first or low second conductivity type.Type: GrantFiled: December 21, 2020Date of Patent: March 7, 2023Assignee: AZUR SPACE Solar Power GmbHInventors: Clemens Waechter, Gregor Keller, Daniel Fuhrmann
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Patent number: 11600794Abstract: A display device is disclosed. In one aspect, the display device includes a flexible substrate capable of being bent in a first direction and an insulating layer including a first opening pattern positioned on the flexible substrate and extending in a second direction crossing the first direction.Type: GrantFiled: April 29, 2021Date of Patent: March 7, 2023Assignee: Samsung Display Co., Ltd.Inventors: Tae Woong Kim, Hyun Woo Koo, Young Gug Seol
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Patent number: 11594673Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.Type: GrantFiled: March 27, 2019Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Noriyuki Sato, Angeline Smith, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Benjamin Buford, Tofizur Rahman, Rohan Patil, Nafees Kabir, Michael Christenson, Ian Young, Hui Jae Yoo, Christopher Wiegand
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Patent number: 11587932Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper part of the air spacer.Type: GrantFiled: June 23, 2021Date of Patent: February 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung Deog Choi, Ji Woon Im
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Patent number: 11587883Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: GrantFiled: February 1, 2021Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
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Patent number: 11581230Abstract: A power semiconductor module includes: at least one semiconductor substrate having a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer; at least one semiconductor body arranged on the first metallization layer; at least one end stop element arranged either on the semiconductor substrate or on one of the at least one semiconductor body and extending from the semiconductor substrate or the respective semiconductor body in a vertical direction that is perpendicular to a top surface of the semiconductor substrate; and a housing at least partly enclosing the semiconductor substrate, the housing including sidewalls and a cover. The housing further includes at least one press-on pin extending from the cover of the housing towards one of the at least one end stop element, and exerting a pressure on the respective end stop element.Type: GrantFiled: May 13, 2021Date of Patent: February 14, 2023Assignee: Infineon Technologies AGInventor: Marco Ludwig